AD9235BCP-65

Overview

The AD9235BCP-65 is a monolithic, single 3 V supply, 12-bit analog-to-digital converter (ADC) operating at a maximum sampling rate of 65 MSPS. It utilizes a multistage differential pipelined architecture with output error correction logic to ensure no missing codes across the full industrial temperature range (-40°C to +85°C). The device integrates a high-performance sample-and-hold amplifier (SHA) and an internal voltage reference. It features a differential input with 500 MHz bandwidth, flexible analog input ranges from 1 V p-p to 2 V p-p, and supports offset binary or two's complement data formats. Power consumption is rated at 300 mW at 65 MSPS.

Feature Summary

• Integrated high-performance sample-and-hold amplifier (SHA) and voltage reference
• Multistage differential pipelined architecture with output error correction logic
• Clock duty cycle stabilizer for maintaining performance under wide clock variations
• Out-of-range (OTR) signal indicating overflow conditions

Applications

• Ultrasound equipment
• IF sampling in communications receivers
• IS-95, CDMA-One, IMT-2000 systems
• Battery-powered instruments
• Low cost digital oscilloscopes

Procurement Notes

Verify the specific suffix 'BCP' corresponds to the 32-lead LFCSP package configuration when sourcing components. Confirm that the '-65' designation matches the required 65 MSPS sampling speed specification. Ensure compatibility with the industrial temperature range requirements for the intended application environment before finalizing procurement.

Selection Notes

Select this component for applications requiring 12-bit resolution at speeds up to 65 MSPS with low power consumption. Consider the 32-lead LFCSP package for space-constrained designs. Evaluate the need for the integrated reference versus external options based on system noise requirements. Verify that the single-ended clock input and DCS functionality align with the available clock source characteristics.

Part Context

The AD9235BCP-65 belongs to the AD9235 family of 12-bit ADCs, which also includes variants operating at 20 MSPS and 40 MSPS. The 'BCP' suffix specifically denotes the 32-lead LFCSP package, distinguishing it from the 28-lead TSSOP option. This family shares a common architectural foundation but varies in throughput capabilities and packaging styles to suit different design constraints.

Replacement Considerations

The pinout is similar to the AD9214-65, allowing for simplified upgrades from 10-bit to 12-bit systems. Check for direct replacements within the Analog Devices portfolio that match the 65 MSPS speed and 12-bit resolution while adhering to the same package and voltage specifications.

FAQ

What is the pipeline delay latency of the AD9235BCP-65?

The AD9235BCP-65 has a fixed pipeline delay latency of 7 cycles.

How does the AD9235 handle out-of-range signals?

An Out-of-Range (OTR) signal indicates when the input exceeds the selected range. This bit can be used in conjunction with the most significant bit to determine if the overflow is high or low.

Can the AD9235BCP-65 operate in single-ended mode?

Yes, the wide bandwidth SHA allows for user-selectable input ranges and offsets, including single-ended applications, although differential operation is typically recommended for optimal performance.