AD9235BRURL7-65

Overview

The AD9235BRURL7-65 is a monolithic, single 3 V supply, 12-bit analog-to-digital converter (ADC) operating at a maximum sampling rate of 65 MSPS. It utilizes a multistage differential pipelined architecture with output error correction logic to ensure no missing codes across the industrial temperature range (-40°C to +85°C). The device features a high-performance sample-and-hold amplifier (SHA) and an on-chip voltage reference. Key electrical specifications include a Signal-to-Noise Ratio (SNR) of 70.5 dBc at Nyquist frequency, a Spurious-Free Dynamic Range (SFDR) of 85 dBc, and a power consumption of 350 mW at full speed. It accepts differential or single-ended analog inputs with a flexible input span of 1 V p-p to 2 V p-p.

Feature Summary

• Integrated high-bandwidth differential sample-and-hold amplifier supporting up to 500 MHz bandwidth.
• Built-in clock duty cycle stabilizer to maintain performance despite wide clock pulse width variations.
• Flexible analog input configuration allowing selectable ranges from 1 V p-p to 2 V p-p.
• On-chip voltage reference with selectable output modes for simplified system design.

Applications

• Ultrasound equipment
• IF sampling in communications receivers
• Battery-powered instruments

Procurement Notes

Verify the specific ordering suffix against the manufacturer's current datasheet revision to confirm package type and tape/reel configuration. Ensure compatibility with the required digital logic voltage levels by checking the DRVDD supply requirements. Confirm that the component meets all necessary environmental and regulatory standards for the intended deployment region before finalizing procurement orders.

Selection Notes

Select this component when a 12-bit resolution and 65 MSPS throughput are required within a low-power, single-supply constraint. Consider the pinout similarity to the AD9214-65 if upgrading existing 10-bit systems. Evaluate the need for the internal reference versus external precision references based on system noise floor requirements and board space limitations.

Part Context

This part belongs to the AD9235 family of 12-bit ADCs, which also includes variants rated for 20 MSPS and 40 MSPS. The BRU designation typically indicates a TSSOP package, while other suffixes may denote LFCSP packages. The family shares a common functional block diagram and architectural approach, differing primarily in maximum conversion rates and packaging options.

Replacement Considerations

Direct pin-compatible replacements within the same family include the AD9235BRUZ-20 and AD9235BRUZ-40, though these operate at lower sampling rates. For higher performance requirements, consider the AD9236 series, but verify pinout compatibility as it differs from the AD9235.

FAQ

What is the function of the OTR pin?

The Out-of-Range (OTR) signal indicates when the analog input exceeds the selected input range. It can be used in conjunction with the most significant bit to determine whether the overflow is a high or low condition.

How does the Clock Duty Cycle Stabilizer (DCS) work?

The DCS compensates for wide variations in the clock duty cycle, ensuring that the ADC maintains excellent overall performance even when the clock pulse widths deviate significantly from the ideal 50% duty cycle.

Can the AD9235 accept single-ended inputs?

Yes, the wide-bandwidth, truly differential SHA allows for user-selectable input ranges and offsets, including single-ended applications, providing flexibility for various system designs.