AD9246BCPZ-105

Overview

The AD9246BCPZ-105 is a monolithic, single 1.8 V supply, 14-bit analog-to-digital converter (ADC) with a maximum sampling rate of 105 MSPS. It features a high-performance sample-and-hold amplifier and an on-chip voltage reference. The device utilizes a multistage differential pipeline architecture with output error correction logic to ensure 14-bit accuracy without missing codes across the full operating temperature range. Key electrical specifications include a signal-to-noise ratio of 71.7 dBc at 70 MHz input and a spurious-free dynamic range of 85 dBc. Power consumption is 395 mW at the maximum data rate.

Feature Summary

• Multistage differential pipeline architecture with output error correction logic for high accuracy
• Integrated sample-and-hold amplifier and on-chip voltage reference
• Flexible digital output formats including offset binary, Gray code, or twos complement
• Clock duty cycle stabilizer to maintain performance over wide clock pulse width variations

Applications

• Ultrasound equipment
• IF sampling in communications receivers
• IS-95, CDMA-One, IMT-2000 systems
• Battery-powered instruments
• Hand-held scopemeters

Procurement Notes

Verify the specific speed grade suffix matches the required conversion rate. Confirm that the LFCSP_VQ package thermal pad is properly soldered to the ground plane to ensure optimal heat dissipation and reliability. Check that the DRVDD supply voltage aligns with the target logic family requirements before integration.

Selection Notes

Select this component when a 14-bit resolution and 105 MSPS sampling rate are required within a low-power constraint. Ensure the system can accommodate the 1.8 V analog supply and separate digital driver supply. Consider pin compatibility with the AD9233 if migrating from a 12-bit architecture is necessary for design flexibility.

Part Context

The AD9246 series includes variants with different maximum sampling rates: 80 MSPS, 105 MSPS, and 125 MSPS. The BCPZ-105 variant specifically denotes the 105 MSPS speed grade within the 48-lead LFCSP_VQ package family. All variants share the same architectural features and pinout, differing primarily in their guaranteed maximum conversion speeds.

Replacement Considerations

The AD9233 is pin-compatible with the AD9246, allowing migration from 12 bits to 14 bits.