AD9460BSVZ-105

Analog To Digital Converters (ADC) Overview

The AD9460BSVZ-105 is a monolithic 16-bit analog-to-digital converter (ADC) with a guaranteed sampling rate of 105 MSPS. It features an on-chip track-and-hold circuit, internal voltage reference, and buffered analog inputs. The device operates with 3.3 V and 5.0 V power supplies and supports both LVDS and CMOS digital outputs. Key performance metrics include a typical SNR of 78.1 dB at 10 MHz input and 76.2 dB at 170 MHz input. Differential nonlinearity (DNL) is typically ±0.5 LSB, while integral nonlinearity (INL) is ±3.0 LSB. The component is housed in a 100-lead TQFP_EP package and functions within an industrial temperature range of -40°C to +85°C.

Analog To Digital Converters (ADC) Feature Summary

• Integrated clock duty cycle stabilizer maintains ADC performance across varying clock pulse widths.
• Configurable output data format selection between offset binary and two's complement modes.
• On-chip reference and high-impedance track-and-hold simplify system design by eliminating external driver components.
• Out-of-range outputs provide indication when the signal exceeds the selected input range.

Analog To Digital Converters (ADC) Applications

• MRI receivers
• Multicarrier, multimode cellular receivers
• Antenna array positioning systems
• Power amplifier linearization
• Broadband wireless communications

Analog To Digital Converters (ADC) Procurement Notes

Verify the specific suffix 'BSVZ-105' against official Analog Devices documentation to confirm the 105 MSPS speed grade and Pb-free TQFP_EP packaging. Ensure that supply voltages match the required 3.3 V and 5.0 V rails for proper operation. Confirm thermal management requirements for the exposed heat sink pad during integration.

Analog To Digital Converters (ADC) Selection Notes

Select this model when a 16-bit resolution and 105 MSPS sampling rate are required for baseband or IF frequencies below 100 MHz. Consider the AD9460BSVZ-80 if an 80 MSPS rate suffices, as it may offer different power characteristics. Evaluate the need for LVDS versus CMOS outputs based on downstream interface compatibility and trace length constraints.

Analog To Digital Converters (ADC) Part Context

This component belongs to the AD9460 family of high-speed, high-resolution ADCs from Analog Devices. The family includes variants optimized for 80 MSPS and 105 MSPS operation. These devices are designed for applications requiring superior signal-to-noise ratios and linearity in instrumentation, medical imaging, and radar receiver architectures.

Analog To Digital Converters (ADC) Replacement Considerations

The AD9460BSVZ-80 is a confirmed substitute within the same family offering 80 MSPS operation. Verify pinout compatibility and ensure that the reduced sampling rate meets system timing requirements before substitution.

Analog To Digital Converters (ADC) FAQ

What is the pipeline delay latency of the AD9460BSVZ-105?

The pipeline delay latency is 13 clock cycles for both CMOS and LVDS output modes.

How does the SFDR control pin affect performance?

Connecting the SFDR pin to AGND optimizes spurious-free dynamic range for analog input frequencies up to 200 MHz. Connecting it to AVDD1 optimizes performance for frequencies above 200 MHz but increases AVDD2 power dissipation.

What is the aperture uncertainty specification?

The aperture uncertainty (jitter) is specified as 60 fs rms.