AD9572ACPZLVD-R7

Overview

The AD9572ACPZLVD-R7 is a fully integrated dual VCO/PLL clock generator optimized for Fiber Channel applications. It provides seven outputs: one 156.25 MHz, two 106.25 MHz, one selectable 100 MHz or 125 MHz, one 33.33 MHz CMOS, and one 25 MHz reference copy. The device operates on a single 3.3 V supply within the -40°C to +85°C range. Key electrical parameters include 0.19 ps rms jitter at 156.25 MHz (1.875 MHz to 20 MHz) and 0.22 ps rms jitter at 106.25 MHz (0.637 MHz to 10 MHz). Outputs are configurable as LVPECL or LVDS via strapping pins.

Feature Summary

• Dual PLL cores with integrated loop filters and LDOs
• Low jitter performance: 0.19 ps rms at 156.25 MHz
• Seven clock outputs including 156.25 MHz, 106.25 MHz, and 33.33 MHz
• Configurable LVPECL or LVDS output formats

Applications

• Fiber Channel line cards
• Fiber Channel switches and routers
• Gigabit Ethernet support circuits

Procurement Notes

Verify the R7 suffix indicates reel packaging containing 750 units per factory pack. Confirm the LVD designation corresponds to the specific voltage and temperature grade (-40°C to +85°C). Ensure compatibility with the 40-lead LFCSP footprint during procurement planning.

Selection Notes

Select this component when designing Fiber Channel interfaces requiring precise 106.25 MHz and 156.25 MHz clocks. Choose between LVPECL and LVDS output drivers based on system termination requirements using the FREQSEL pin. Ensure the design accommodates the 40-lead LFCSP package thermal dissipation characteristics.

Part Context

This part belongs to the AD9572 series of clock generators. The ACPZLVD-R7 variant specifically denotes the lead-free, RoHS-compliant version in a 40-lead LFCSP package supplied in a reel format. It shares the core architecture with tray-packaged versions but differs in shipping configuration.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.