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Product Detailed Parameters
- Description:IC CLOCK GENERATOR 40LFCSP
- Series:-
- Package:Tape & Reel (TR)
- Mfr:Analog Devices Inc.
- PLL:Yes
- Input:Crystal
- Output:CMOS, LVDS, LVPECL
- Number of Circuits:1
- Ratio - Input:Output:1:07
- Differential - Input:Output:No/Yes
- Frequency - Max:156.25MHz
- Divider/Multiplier:Yes/No
- Voltage - Supply:2.97V ~ 3.63V
- Operating Temperature:-40°C ~ 85°C
- Mounting Type:Surface Mount
- Package / Case:40-WFQFN Exposed Pad, CSP
- Supplier Device Package:40-LFCSP-WQ (6x6)
- Type:Clock Generator, Fanout Distribution, Multiplexer
- Grade:-
- Qualification:-
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Overview
The AD9572ACPZLVD-RL is a fully integrated dual VCO/PLL clock generator designed for Fiber Channel and Ethernet applications. It provides seven clock outputs: one 156.25 MHz, two 106.25 MHz, one selectable 100 MHz or 125 MHz, one 33.33 MHz, and one 25 MHz copy. The device operates from a single 3.3 V supply within a −40°C to +85°C temperature range. Key electrical specifications include an input reference frequency of 25 MHz and output jitter performance of 0.19 ps rms (1.875 MHz to 20 MHz) at 156.25 MHz LVDS. Power dissipation is 0.71 W in LVDS mode and 1.07 W in LVPECL mode.
Feature Summary
- Dual PLL cores with integrated loop filters and LDOs
- Seven clock outputs including 156.25 MHz, 106.25 MHz, and 33.33 MHz
- Low jitter performance: 0.19 ps rms at 156.25 MHz (LVDS)
- Configurable output formats: LVPECL or LVDS
Applications
- Fiber Channel line cards, switches, and routers
- Gigabit Ethernet support systems
- PCIe infrastructure clocking
Procurement Notes
Verify the component is sourced from authorized Analog Devices distributors to ensure authenticity. Confirm the package type matches the 40-lead, 6 mm × 6 mm LFCSP specification. Check that the operating temperature range meets the required industrial standard of −40°C to +85°C. Ensure the power supply voltage aligns with the specified 3.3 V requirement.
Selection Notes
Select this component when low phase noise and jitter are critical for network synchronization. Choose between LVPECL and LVDS output formats based on system interface requirements. Verify that the preset divide ratios for 106.25 MHz, 156.25 MHz, and other frequencies match the application needs without requiring external programming.
Part Context
This part belongs to the AD9572 series of clock generators. It is specifically optimized for high-performance networking applications like Fiber Channel and Gigabit Ethernet. The device integrates multiple PLL cores and output buffers into a compact LFCSP package, reducing board space and design complexity compared to discrete solutions.
Replacement Considerations
Public confirmed substitute part numbers are not available in the provided documentation.
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