AD9575ARUZLVD

Overview

The AD9575ARUZLVD is a dual-output network clock generator featuring an integrated VCO/PLL core optimized for low jitter performance. It operates on a single 3.3 V supply within the -40°C to +85°C temperature range and utilizes a 16-lead TSSOP package. The device accepts external crystals at 19.44 MHz, 25 MHz, or 25.78125 MHz to generate output frequencies up to 312.5 MHz via pin-selectable divide ratios. This specific variant provides LVDS output format with typical rms jitter of 0.39 ps (12 kHz to 20 MHz) at 156.25 MHz.

Feature Summary

• Integrated VCO/PLL core with no external loop filter required
• Pin-programmable output frequencies including 100 MHz, 156.25 MHz, and 312.5 MHz
• Low phase noise: -123 dBc/Hz at 1 kHz offset for 100 MHz output
• LVDS output format with 3.5 mA default current drive

Applications

• GbE/FC/SONET line cards
• Switches and routers
• CPU/PCI-E applications

Procurement Notes

Verify the ordering suffix LVD confirms the LVDS output configuration against the manufacturer's Ordering Guide. Confirm the package option RU-16 matches the required 16-lead TSSOP footprint. Ensure the temperature grade A covers the operational environment requirements of -40°C to +85°C.

Selection Notes

Select this component when LVDS signaling is required for the primary clock output. Compare jitter specifications across different output frequencies if operating at 106.25 MHz or 312.5 MHz. Verify that the internal VCO range (2.488 GHz to 2.55 GHz) supports the desired frequency translation from the selected crystal reference.

Part Context

The AD9575 series includes variants with different output formats. The ARUZPEC suffix denotes LVPECL outputs, while the ARUZLVD suffix specifies LVDS outputs. Both share the same PLL architecture and package dimensions but differ in output buffer design and termination requirements.

Replacement Considerations

The AD9575ARUZPEC serves as a functional alternative if LVPECL outputs are acceptable instead of LVDS. No other direct cross-model replacements are documented in the provided datasheet.

FAQ

What is the maximum output frequency supported by the AD9575?

The maximum output frequency is 312.5 MHz.

Does the AD9575 require an external loop filter?

No, the AD9575 features an integrated third-order loop filter, eliminating the need for external components.

How is the output frequency selected?

Output frequencies are determined by the logic states of the SEL0 and SEL1 pins, which configure the feedback and output divider ratios.