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AD9613BCPZRL7-170 is listed in the Analog To Digital Converters (ADC) range at ChipApex. The manufacturer field lists Analog Devices Inc.. Its product description is IC ADC 12BIT PIPELINED 64LFCSP. Review the specifications below when checking this part for your BOM.
The AD9613BCPZRL7-170 is a dual-channel, 12-bit analog-to-digital converter (ADC) from Analog Devices Inc., designed for high-speed data acquisition. It operates at a maximum sampling rate of 170 MSPS with a nominal 1.8 V supply voltage. The device features a multistage differential pipelined architecture and includes an integrated voltage reference and duty cycle stabilizer. Digital outputs are provided in LVDS format via a 64-lead LFCSP package. It supports industrial operating temperatures ranging from -40°C to +85°C.
Verify the specific speed grade suffix (-170) against the required system sampling rate before procurement. Confirm that the reel packaging matches the handling requirements of the assembly line. Ensure the component meets RoHS compliance standards applicable to the target market. Cross-reference the ordering code with the manufacturer's current production status to avoid obsolescence risks.
Select this variant when a 170 MSPS sampling rate is sufficient for the application bandwidth. Consider the pin compatibility with AD9643, AD6649, and AD6643 if future migration to higher resolution or different architectures is planned. Evaluate the power consumption specifications against thermal constraints within the 64-lead LFCSP package.
This part belongs to the AD9613 family of dual 12-bit ADCs, which also includes variants supporting 210 MSPS and 250 MSPS speeds. The -170 designation specifically indicates the lower speed grade optimized for applications where 170 MSPS provides adequate Nyquist zone coverage. The BCPZRL7 suffix denotes the lead-free LFCSP package with reel tape-and-reel packaging.
The AD9613BCPZRL7-210 and AD9613BCPZRL7-250 are pin-compatible alternatives offering higher sampling rates. These can be used as replacements if the system design allows for the increased speed without modification to the PCB layout or clocking infrastructure.
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