AD9695BCPZ-1300

Overview

The AD9695BCPZ-1300 is a dual-channel, 14-bit analog-to-digital converter (ADC) operating at sampling rates up to 1300 MSPS. It features a multistage differential pipelined architecture with integrated output error correction logic and on-chip buffers. The device supports direct sampling of wideband analog signals up to 2 GHz. Key specifications include a typical Signal-to-Noise Ratio (SNR) of 65.6 dBFS at 172 MHz, a full power bandwidth of 2 GHz, and total power consumption of 1.6 W at maximum speed. It utilizes JESD204B Subclass 1 serial outputs with lane rates up to 16 Gbps and includes two digital downconverters per channel.

Feature Summary

• Dual-channel 14-bit ADC with integrated digital downconverters and crossbar multiplexers for flexible signal processing.
• Supports high-speed JESD204B serialization with lane rates up to 16 Gbps and multi-device synchronization capabilities.
• Features programmable fast overrange detection and signal monitoring blocks to simplify automatic gain control implementation.
• Includes an internal voltage reference and on-chip temperature diode for system thermal management.

Applications

• Communications diversity multiband and multimode digital receivers
• Instrumentation oscilloscopes and spectrum analyzers
• Radars and electronic support measures

Procurement Notes

Verify the specific speed grade suffix (1300 vs 625) against design requirements, as performance metrics differ between variants. Confirm that the LFCSP-64 package footprint matches the PCB layout guidelines provided in the datasheet. Ensure supply voltages align with the specified AVDD and DVDD rails before ordering.

Selection Notes

Select this component for applications requiring direct sampling of RF signals up to 2 GHz with low power consumption. Evaluate the need for integrated DDCs versus external processing to optimize system complexity. Consider the 1300 MSPS speed grade if higher bandwidth or SNR performance is required compared to the 625 MSPS variant.

Part Context

This part belongs to the Analog Devices AD9695 family of high-speed ADCs. It shares architectural similarities with the AD9690, AD9691, and AD9694 but offers distinct channel counts and sampling speeds. The BC prefix indicates a specific commercial temperature range and packaging configuration within the broader product line.

Replacement Considerations

The AD9695BCPZ-625 is a lower-speed variant of the same device family. Verify compatibility regarding pinout and register settings if substituting, noting differences in maximum sample rate and associated power consumption profiles.

FAQ

What is the maximum lane rate supported by the JESD204B interface?

The AD9695 supports JESD204B lane rates up to 16 Gbps.

How many digital downconverters are included per ADC channel?

Each ADC channel contains two integrated digital downconverters (DDCs).

What is the typical SNR at 172 MHz input frequency?

The typical Signal-to-Noise Ratio (SNR) is 65.6 dBFS at an input frequency of 172 MHz with a 1.59 V p-p input range.