AD9844AJSTRL

Overview

The AD9844AJSTRL is a complete 12-bit, 20 MSPS CCD signal processor designed for interlaced and progressive scan area CCD arrays. It integrates a 20 MHz Correlated Double Sampler (CDS) with variable gain from -2 dB to 10 dB, a 10-bit Variable Gain Amplifier (VGA) providing 2 dB to 36 dB gain, and a 12-bit A/D converter with a 2.0 V full-scale input range. The device operates on a single 3 V supply, dissipating approximately 78 mW in normal operation. Key features include low noise clamp circuits, an analog preblanking function, auxiliary inputs, and configuration via a 3-wire serial digital interface.

Feature Summary

• Integrates a 20 MHz Correlated Double Sampler (CDS) with digitally programmable gain control.
• Includes a high-resolution Variable Gain Amplifier (VGA) for precise signal conditioning.
• Features dedicated auxiliary input channels for processing analog video signals.
• Utilizes a 3-wire serial digital interface for internal register programming.

Applications

• Digital Still Cameras
• Digital Video Camcorders
• PC Cameras

Procurement Notes

Verify the component authenticity by checking the marking code against the official datasheet specifications. Confirm that the package type matches the 48-lead LQFP description. Ensure the temperature range meets the operational requirements of the target application environment before finalizing procurement decisions.

Selection Notes

Select this component when interfacing with CCD sensors requiring integrated DC restoration and correlated double sampling. The 2 V ADC full-scale range offers improved noise performance compared to 1 V systems. Consider the 3-wire serial interface compatibility with the host microcontroller or ASIC for system integration.

Part Context

The AD9844A serves as an Analog Front End (AFE) for CCD image sensors. It processes raw pixel data through DC restoration, CDS, gain adjustment, and black level correction before digitization. This integration simplifies design-in by consolidating multiple analog signal conditioning functions into a single chip.

Replacement Considerations

The AD9843 is a related predecessor model. Verify pinout compatibility and functional differences, such as reset mechanisms, when considering substitution. Ensure the replacement supports the required CCD timing and signal chain specifications.

FAQ

What is the default CDS gain setting?

The default CDS gain is 4 dB when the CDS Gain Enable bit in the Control Register is disabled.

How is the VGA gain calculated?

Gain is determined by two equations based on the register code: Code 0–511 uses a logarithmic shape, while Code 512–1023 follows a linear-in-dB characteristic.

What is the power consumption in Total Power-Down mode?

The total power consumption in Total Power-Down mode is 1 mW.