AD9847KST

Overview

The AD9847KST is a 10-bit CCD signal processor with an integrated timing driver, packaged in a 48-lead LQFP. It operates within a temperature range of -20°C to +85°C and supports a maximum clock rate of 40 MHz. The analog front end includes a Correlated Double Sampler (CDS), a Pixel Gain Amplifier (PxGA) with -2 dB to +10 dB gain, and a Variable Gain Amplifier (VGA) providing 2 dB to 36 dB gain. The device features a 10-bit A/D converter with a full-scale input voltage of 2.0 V. Power supply requirements include AVDD at 2.7 V to 3.6 V and DVDD for H-drivers at 3.0 V to 5.5 V.

Feature Summary

• Integrated Precision Timing core allows high-speed clock adjustment with approximately 500 ps resolution at 40 MHz.
• On-chip 5 V horizontal and RG drivers provide direct connection capability to CCD inputs.
• Programmable timing generation supports flexible control over horizontal CCD readout and AFE correlated double sampling.

Applications

• Digital Still Cameras

Procurement Notes

Verify the specific suffix KST against official documentation to confirm package type and temperature rating. Confirm availability status as distributors may list discontinued or obsolete inventory. Ensure ESD precautions are observed during handling due to device sensitivity.

Selection Notes

Select this component for applications requiring a highly integrated CCD signal processing solution with on-chip timing generation. Verify that the required pixel clock frequency does not exceed 40 MHz. Ensure the system design accommodates the specified power supply voltages for analog and digital domains.

Part Context

The AD9847 belongs to Analog Devices' family of CCD signal processors designed for digital imaging applications. It combines analog front-end processing with digital timing control in a single package. The KST suffix typically denotes the Thin Plastic Quad Flatpack (LQFP) package variant suitable for space-constrained designs.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Consult Analog Devices technical support for current replacement recommendations if the AD9847KST is unavailable.

FAQ

What is the edge resolution of the Precision Timing core?

The Precision Timing core divides the master clock period into 48 steps, providing an edge resolution of t_CLI/48, which is approximately 500 ps at 40 MHz.

How is the drive current for the H-drivers adjusted?

The H-driver current is adjustable using the DRV registers in 3.5 mA increments, ranging from OFF (0) to 24.5 mA (7).

What is the default gain setting for the PxGA?

The default setting for the Pixel Gain Amplifier (PxGA) is Med Gain (0), which corresponds to 4 dB.