AD9851BRSZ

Overview

The AD9851BRS is a CMOS Direct Digital Synthesizer (DDS) featuring an 180 MHz clock rate and a selectable 6× reference clock multiplier. It integrates a high-performance 10-bit DAC and a high-speed comparator with hysteresis. The device accepts a 32-bit frequency tuning word, enabling precise frequency synthesis up to 72 MHz analog output or 200 MHz square wave output. Operating on a single supply from 2.7 V to 5.25 V, it supports simplified parallel or serial control interfaces. Key electrical specifications include a wideband SFDR of >43 dB at 70 MHz and residual phase noise of -132 dBc/Hz.

Feature Summary

• Integrates a 6× reference clock multiplier to reduce external oscillator requirements.
• Provides dual output paths for high-resolution analog sine waves and low-jitter digital square waves.
• Supports asynchronous loading of 40-bit control words via parallel or serial interfaces.
• Includes 5-bit phase modulation and offset capability for agile signal generation.

Applications

• Frequency-agile local oscillators for frequency mixing and multiplying.
• Digitally programmable divide-by-N functions in PLL systems.
• High-quality all-digital RF frequency modulation generation.
• Chip rate clock generators in spread spectrum receivers.

Procurement Notes

Verify the ordering suffix RS-28 corresponds to the Shrink Small Outline Package (SSOP) with 28 pins. Confirm the temperature range is industrial (-40°C to +85°C). Ensure the component matches the REV. D datasheet specifications for voltage levels and timing characteristics before integration into the design.

Selection Notes

Select this model when an 180 MHz system clock is required for higher output frequency ranges compared to lower-speed DDS variants. The integrated 6× multiplier allows the use of lower-frequency reference clocks, simplifying board layout. Verify that the SSOP package option meets the thermal and physical constraints of the target application.

Part Context

The AD9851 is part of Analog Devices' family of direct digital synthesizers, designed for applications requiring fast frequency switching and high spectral purity. It utilizes a proprietary angle rotation algorithm to convert phase accumulator data to DAC amplitude, minimizing ROM size while maintaining performance. This specific variant is optimized for industrial temperature ranges and standard surface-mount assembly.

Replacement Considerations

The DS852 is documented as a potential replacement for the AD9851. Evaluate the DS852 based on its higher clock speed capabilities and power consumption differences. Ensure interface compatibility and verify that the substitute meets the specific jitter and SFDR requirements of the original design.

FAQ

How does the 6× REFCLK multiplier affect the input clock frequency?

When enabled, the internal multiplier multiplies the external reference clock frequency by six to generate the system clock. For example, a 30 MHz input results in a 180 MHz system clock.

What is the maximum toggle frequency of the comparator output?

The comparator can toggle at frequencies up to 200 MHz when driven by a 1 V p-p input sine wave.

How is the DAC full-scale output current determined?

The full-scale output current is set by an external resistor connected to the RSET pin. The relationship is defined by IOUT = 39.93 / RSET.