AD9920ABBCZRL

Overview

The AD9920ABBCZRL is a highly integrated CCD signal processor designed for digital still camera applications. It features a complete analog front end with a 12-bit, 40.5 MHz ADC, a programmable timing generator, and a 19-channel vertical driver. The device includes a Precision Timing core with approximately 400 ps resolution at 40.5 MHz operation. Key specifications include an operating temperature range of −25°C to +85°C, AVDD/TCVDD/DVDD supplies of 1.6 V to 2.0 V, and CLIVDD/RGVDD/HVDD supplies of 1.6 V to 3.6 V. It is housed in a 105-ball, 8 mm × 8 mm CSP_BGA package.

Feature Summary

• Integrated 19-channel vertical driver supporting up to 24 programmable vertical clock signals
• Correlated double sampler (CDS) with selectable gains of −3 dB, 0 dB, +3 dB, and +6 dB
• Complete on-chip timing generator with Precision Timing core (~400 ps resolution)
• On-chip 1.8 V low dropout (LDO) regulator and six general-purpose outputs (GPOs)

Applications

• Digital still cameras

Procurement Notes

Verify the specific suffix 'BBCZRL' against the manufacturer's current ordering guide to confirm availability and packaging details. Check for any recent product change notices or lifecycle status updates directly from Analog Devices documentation before procurement planning.

Selection Notes

Select this component when designing systems requiring a fully integrated CCD interface with precise timing control. Ensure supply voltages match the specified ranges: 1.6 V to 2.0 V for AFE/Timing/Digital cores and up to 3.6 V for drivers and I/O. Verify that the 105-ball CSP_BGA package footprint fits the PCB layout constraints.

Part Context

This part belongs to the AD9920A family of CCD signal processors. It serves as a specialized analog front-end solution for converting CCD sensor signals into digital data while managing complex clocking sequences required by advanced CCD imagers.

Replacement Considerations

Consult the AD9920A datasheet Ordering Guide for confirmed substitute part numbers within the same family. No external cross-model substitutes are verified in the provided source material.