ADAU1328BSTZ

Overview

The ADAU1328BSTZ is a high-performance, single-chip audio codec manufactured by Analog Devices Inc. It features two differential analog-to-digital converters (ADCs) and eight single-ended digital-to-analog converters (DACs). The device supports sample rates from 8 kHz to 192 kHz with 24-bit resolution. It operates on a single 3.3 V supply and includes an on-chip phase-locked loop (PLL) for clock generation. Key performance metrics include a dynamic range of 107 dB for ADCs and 108 dB for DACs, with a total harmonic distortion plus noise of -94 dB. The component is housed in a 48-lead LQFP package.

Feature Summary

• Integrates a low EMI design architecture utilizing continuous time converter architectures and on-chip PLL to minimize electromagnetic interference.
• Provides software-controllable clickless mute, volume control with autoramp, and power-down modes for flexible system management.
• Supports multiple serial data formats including I2S, left justified, right justified, and TDM modes for versatile digital audio interface compatibility.

Applications

• Home theater systems
• Set-top boxes
• Digital audio effects processors

Procurement Notes

Verify the specific suffix BSTZ against the manufacturer's ordering guide to confirm the package type and temperature range. Confirm RoHS compliance status through official documentation. Check for end-of-life notifications or obsolescence warnings prior to finalizing procurement plans.

Selection Notes

Select this component for applications requiring multi-channel output with differential stereo inputs. Ensure the design accommodates the 3.3 V supply requirement and provides adequate bypassing for AVDD and DVDD pins. Verify that the host processor supports the required SPI control port and serial data interface protocols.

Part Context

This part belongs to the ADAU1328 family of audio codecs. Other members of this family may offer differential DAC outputs instead of single-ended configurations. The datasheet indicates availability in a 48-lead LQFP package for the single-ended output version.

Replacement Considerations

Consult the manufacturer's current product selection guide for direct replacements or updated revisions. Verify pinout compatibility and electrical specifications if substituting with other members of the ADAU1328 family or newer generations.

FAQ

How does the ADAU1328 handle master clock generation?

The device features an on-chip PLL that can generate the master clock from the LR clock or an external crystal. It can also operate in direct master clock mode, eliminating the need for a separate high-frequency clock source.

What is the recommended input configuration for the ADCs?

For best performance, the ADCs should be driven from a differential signal source. Each input pin should be isolated using a series connected external 100 Ω resistor and a 1 nF capacitor to ground.

Can the internal voltage reference be disabled?

Yes, the internal voltage reference can be disabled via the PLL and Clock Control 1 Register. This allows the FILTR pin to be driven by an external source to scale the DAC output level.