ADC09SJ1300AAVTQ1

Analog To Digital Converters (ADC) Overview

The ADC09SJ1300AAVTQ1 is a single-channel, 9-bit analog-to-digital converter (ADC) from Texas Instruments. It operates at a maximum sampling rate of 1.3 GSPS with a full-power input bandwidth of 6 GHz. The device features a differential full-scale input voltage of 800 mVPP-DIFF and utilizes an internal non-interleaved architecture. Performance specifications include a signal-to-noise ratio (SNR) of 53.5 dBFS and an effective number of bits (ENOB) of 8.5 bits at 100 MHz input frequency. Power consumption is rated at 940 mW when operating at 1 GSPS. The component is housed in a 144-ball FCBGA package.

Analog To Digital Converters (ADC) Feature Summary

• AEC-Q100 qualified for automotive applications across the –40°C to +125°C temperature range.
• Integrated JESD204C serial interface supporting up to four SerDes lanes with baud-rates reaching 17.16 Gbps.
• Includes an optional internal phase-locked loop (PLL) with a voltage-controlled oscillator (VCO) for sampling clock generation.
• Features timestamp inputs and outputs designed specifically for synchronization in pulsed systems.

Analog To Digital Converters (ADC) Applications

• Light detection and ranging (LiDAR)
• Frequency modulated continuous wave (FMCW) LiDAR systems
• Pulse-based LiDAR systems

Analog To Digital Converters (ADC) Procurement Notes

Verify that the specific ordering suffix matches the required package type and temperature grade. Confirm that the AAV suffix corresponds to the 144-ball FCBGA package dimensions. Ensure compatibility with the intended system power supply voltages of 1.1 V and 1.9 V before finalizing procurement orders.

Analog To Digital Converters (ADC) Selection Notes

Select this model for applications requiring high-speed single-channel conversion with low power consumption. Verify that the 9-bit resolution meets the dynamic range requirements for the target signal. Ensure the host system can support the JESD204C interface protocols and provides adequate clocking infrastructure for the 1.3 GSPS operation.

Analog To Digital Converters (ADC) Part Context

This component belongs to the ADC09xJ1300-Q1 family, which includes quad and dual-channel variants. All members share the same 1.3 GSPS sampling rate, 9-bit resolution, and 6 GHz input bandwidth. The primary distinction lies in the channel count and the corresponding number of available JESD204C output lanes.

Analog To Digital Converters (ADC) Replacement Considerations

Direct replacements within the same family include the ADC09DJ1300-Q1 (dual-channel) and ADC09QJ1300-Q1 (quad-channel). These parts share identical electrical characteristics but differ in channel count and pinout configurations.

Analog To Digital Converters (ADC) FAQ

What is the maximum baud-rate supported by the JESD204C interface?

The maximum baud-rate supported by the JESD204C interface is 17.16 Gbps.

Does the device support deterministic latency?

Yes, the device supports Subclass-1 mode for deterministic latency over the JESD204C interface.

How is the sampling clock generated if not provided externally?

The device features an optional internal phase-locked loop (PLL) with an integrated voltage-controlled oscillator (VCO) capable of generating frequencies between 7.2 GHz and 8.2 GHz.