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Product Detailed Parameters
- Description：IC COMPARATOR 2 W/LATCH 16QSOP
- Series：-
- Mfr：Analog Devices Inc.
- Package：Tube,Tube
- Type：with Latch
- Number of Elements：2
- Output Type：Complementary, Differential, Open-Emitter, PECL
- Voltage - Supply, Single/Dual (±)：±4.75V ~ 5.25V
- Voltage - Input Offset (Max)：2mV @ -5.2V,5V
- Current - Input Bias (Max)：3µA @ -5.2V,5V
- Current - Output (Typ)：30mA
- Current - Quiescent (Max)：5mA, 28mA, 13mA
- CMRR, PSRR (Typ)：80dB CMRR, 85dB PSRR
- Propagation Delay (Max)：0.83ns
- Hysteresis：±1mV
- Operating Temperature：-40°C ~ 85°C
- Package / Case：16-SSOP (0.154", 3.90mm Width)
- Mounting Type：Surface Mount
- Supplier Device Package：16-QSOP
- Grade：-
- Qualification：-
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Overview
The ADCMP561BRQ is a dual high-speed PECL comparator fabricated on Analog Devices' proprietary XFCB process. It features a 700 ps propagation delay with less than 75 ps overdrive dispersion. The device operates within an input common-mode range of -2.0 V to +3.0 V and provides differential latch control for track-and-hold or sample-and-hold modes. Outputs are complementary digital signals compatible with PECL 10K/10KH logic, capable of driving 50 Ω transmission lines terminated to VDD - 2 V. Power supply rejection exceeds 85 dB.
Feature Summary
- Differential PECL-compatible outputs
- Robust input protection
- Internal latch pull-up resistors
- ESD protection > 4 kV HBM
Applications
- Automatic test equipment
- High speed instrumentation
- Scope and logic analyzer front ends
- Window comparators
- High speed line receivers
Procurement Notes
Verify the specific ordering suffix against official documentation to confirm package type and temperature rating. Confirm that the component matches the exact part number required for your design specifications. Check for any recent datasheet revisions that may impact electrical characteristics or pin configurations before finalizing procurement decisions.
Selection Notes
Select this component for applications requiring consistent propagation delay across varying overdrive conditions. Ensure the design accommodates the specified dual-supply voltage requirements and utilizes proper PECL termination techniques. Consider the 16-lead QSOP package constraints for thermal management and layout in high-speed circuit designs.
Part Context
This device belongs to the ADCMP561/ADCMP562 family of high-speed comparators. While the ADCMP562 includes a programmable hysteresis pin, the ADCMP561 variant does not. Both share identical core performance metrics regarding speed and power supply rejection, differing primarily in the availability of external hysteresis control.
Replacement Considerations
The ADCMP561BRQZ is the direct equivalent replacement for the ADCMP561BRQ, sharing identical electrical specifications and pinout configuration.
