ADCMP562BRQZ-RL7

Overview

The ADCMP562BRQZ-RL7 is a dual high-speed PECL comparator fabricated on Analog Devices' proprietary XFCB process. It features a 700 ps propagation delay with less than 75 ps overdrive dispersion, ensuring consistent timing across varying input conditions. The device includes differential latch control for track-and-hold or sample-and-hold modes and offers programmable hysteresis via dedicated pins. Outputs are complementary digital signals compatible with PECL 10K/10KH logic families, providing sufficient drive current to directly drive 50 Ω transmission lines terminated to VDD − 2 V.

Feature Summary

• Differential PECL-compatible outputs fully compatible with PECL 10K and 10KH logic families
• Separate programmable hysteresis pins allow flexible noise immunity adjustment
• Differential latch control enables tracking, track-and-hold, or sample-and-hold operation
• Robust input protection with ESD ratings exceeding 4 kV HBM and 200 V MM

Applications

• Automatic test equipment
• High speed instrumentation
• Scope and logic analyzer front ends
• Window comparators
• High speed line receivers

Procurement Notes

Verify the specific ordering suffix RL7 corresponds to the required reel packaging configuration before procurement. Confirm that the RQ-20 package option matches your PCB footprint requirements. Ensure supply voltages align with the specified operating range of +5.0 V, -5.2 V, and +3.3 V logic supply. Check for any recent revision updates in the datasheet that may affect pin compatibility or electrical characteristics.

Selection Notes

Select this component when low propagation delay dispersion is critical for timing accuracy under varying overdrive conditions. The ADCMP562 is distinct from the ADCMP561 due to its integrated programmable hysteresis pins, making it suitable for noisy environments. Consider the 20-lead QSOP package dimensions and thermal resistance of 80°C/W in still air for board layout planning. Verify that the input common-mode range of -2.0 V to +3.0 V accommodates your signal levels.

Part Context

The ADCMP562 belongs to the ADCMP561/ADCMP562 family of dual high-speed comparators manufactured by Analog Devices. These devices utilize the XFCB process to achieve high performance metrics such as 1.5 GHz equivalent input rise time bandwidth. The family shares similar electrical characteristics but differs in package count and feature availability, specifically regarding hysteresis control options.

Replacement Considerations

The ADCMP561 serves as a functional substitute if programmable hysteresis is not required, though it utilizes a 16-lead QSOP package instead of the 20-lead variant.

FAQ

How is hysteresis configured on the ADCMP562?

Hysteresis is generated through the programmable hysteresis pins (HYSA and HYSB). A resistor connected from the HYS pin to ground creates a current that generates symmetrical hysteresis independent of output swing.

What is the default state of the latch inputs if left unconnected?

If the Latch Enable inputs are left open or unconnected, the internal pull-up resistors set the latch in compare mode, allowing the output to track changes at the input.

Can the ADCMP562 directly drive transmission lines?

Yes, the outputs provide sufficient drive current to directly drive transmission lines terminated in 50 Ω to VDD − 2 V without additional buffering.