ADCMP562BRQZ

Overview

The ADCMP562BRQZ is a dual high-speed comparator fabricated on Analog Devices' proprietary XFCB process. It features differential PECL-compatible outputs and operates within an input common-mode range of -2.0 V to +3.0 V. The device provides a typical propagation delay of 700 ps with less than 75 ps overdrive dispersion. It includes programmable hysteresis, differential latch control, and robust input protection. Power supply rejection exceeds 85 dB, and it supports ESD protection greater than 4 kV HBM.

Feature Summary

• Features differential PECL-compatible outputs for direct transmission line driving
• Includes a separate programmable hysteresis pin for noise immunity adjustment
• Provides differential latch control with internal pull-up resistors for tracking or sample-and-hold modes
• Offers robust input protection and power supply rejection exceeding 85 dB

Applications

• Automatic test equipment
• High speed instrumentation
• Scope and logic analyzer front ends
• Window comparators
• Threshold detection

Procurement Notes

Verify the specific package option (RQ-20) and temperature grade (Industrial, -40°C to +85°C) against project requirements. Confirm that the ordering suffix matches the desired reel or tube configuration. Ensure compatibility with the required logic supply voltage and check for any recent datasheet revisions that may impact design parameters.

Selection Notes

Select this component when low propagation delay dispersion is critical for timing accuracy. The ADCMP562 is suitable for applications requiring programmable hysteresis via an external resistor or current source. Consider its differential latch capability if track-and-hold functionality is needed. Verify that the PECL output interface aligns with downstream logic families such as PECL 10K or 10KH.

Part Context

The ADCMP562BRQZ belongs to the ADCMP561/ADCMP562 family of high-speed comparators. Unlike the ADCMP561, which lacks hysteresis control, the ADCMP562 includes dedicated pins for programmable hysteresis. Both devices share similar electrical characteristics but differ in pin count and package options, with the ADCMP562 utilizing a 20-lead QSOP format.

Replacement Considerations

The ADCMP561BRQZ serves as a functional substitute if programmable hysteresis is not required. Note that the ADCMP561 uses a 16-lead QSOP package, necessitating layout adjustments compared to the 20-lead ADCMP562. Electrical performance remains comparable regarding propagation delay and output drive capabilities.

FAQ

How is hysteresis configured on the ADCMP562?

Hysteresis is generated through the programmable HYS pin. Connecting a resistor from the HYS pin to ground creates a current that sets the hysteresis level. Alternatively, a current source can be applied to the HYS pin to achieve the desired hysteresis value.

What is the function of the LATCH ENABLE inputs?

The LATCH ENABLE inputs allow the comparator to operate in compare mode or latch mode. When left open or driven to specific logic levels, the device defaults to compare mode. Driving these inputs enables tracking, track-and-hold, or sample-and-hold operations by capturing the input state at a specific time.