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The ADDI9023BBCZRL is a 12-channel vertical driver for charge-coupled device (CCD) imaging applications. It integrates eight three-level drivers and four two-level drivers, supporting up to nine individual vertical timing phases and eight shift gate signals. A dedicated substrate clock channel is included. The input logic operates within a 1.6 V to 3.6 V range, while output drivers support −9.5 V to +15.5 V ranges. Typical load drive capability per channel is 3 nF. The component is specified over an operating temperature range of −25°C to +85°C and utilizes a 6 mm × 6 mm CSP_BGA package with a 0.65 mm pitch.
Verify the specific ordering suffix RL indicates tape and reel packaging when sourcing components. Confirm RoHS compliance status as indicated by the Z suffix in the part number. Ensure compatibility with the required 40-lead CSP_BGA footprint during procurement planning. Cross-reference the manufacturer's latest documentation for any updates regarding supply status or lifecycle changes before finalizing orders.
Select this component for designs requiring precise vertical timing control for CCD sensors. Evaluate the power supply requirements, specifically the need for VH, VL, VM, and VDD rails. Consider the thermal resistance characteristics of the CSP_BGA package for heat dissipation. Verify that the input logic voltage levels match the system's timing generator outputs. Assess the load capacitance requirements against the typical 3 nF drive capability.
The ADDI9023 belongs to Analog Devices' family of display drivers and controllers designed for imaging systems. This specific model focuses on vertical driving capabilities for CCD architectures. The BBCZ variant denotes the standard commercial/industrial temperature range and RoHS-compliant construction. The RL suffix differentiates the shipping format from the tray-packaged version.
The ADDI9023BBCZ is a pin-compatible alternative differing only in packaging format.
The VDREN pin acts as the V-driver enable signal. It must be held low during power-up until supplies settle, then taken high to enable the vertical driver outputs for normal operation.
Three-level outputs (V1A to V5) are controlled by pairs of inputs (e.g., XV1 and XSG1). Specific combinations of Low and High logic states on these inputs determine whether the output switches between VH, VM, or VL voltages.