ADEL2020AN

Overview

The ADEL2020AN is a current feedback amplifier in an 8-lead PDIP package, operating from ±3.0 V to ±18 V supplies within the –40 °C to +85 °C industrial temperature range. It delivers a 90 MHz –3 dB bandwidth at unity gain and a 500 V/µs slew rate with a 60 ns settling time to 0.1%. The device features low input voltage noise of 2.9 nV/√Hz and quiescent current of 6.8 mA, reducing to 2.1 mA in power-down mode. It includes a high-performance disable function with 100 ns turn-off time and maintains differential gain and phase errors below 0.05% and 0.05° for video applications.

Feature Summary

• Optimized for high-speed video line driving with minimal differential gain and phase distortion.
• Integrated disable pin enables rapid output isolation and significant power reduction.
• Current feedback architecture provides wide bandwidth independent of closed-loop gain.

Applications

• Video line drivers
• High-speed data acquisition systems
• Signal conditioning circuits

Procurement Notes

Verify the specific ordering suffix AN corresponds to the 8-lead PDIP package and industrial temperature range. Confirm that the component meets RoHS requirements if applicable to your manufacturing standards. Ensure proper ESD handling procedures are followed during assembly due to the sensitivity of the internal circuitry.

Selection Notes

Select this component when designing circuits requiring high slew rates and wide bandwidths with low power consumption. The current feedback topology necessitates careful selection of feedback resistors to maintain stability and optimal frequency response across varying supply voltages.

Part Context

This part belongs to the ADEL2020 series, which serves as an improved second source to the EL2020. The series offers enhanced dynamic specifications, lower power supply current, and reduced offset voltage compared to its predecessor, available in both PDIP and SOIC packages.

Replacement Considerations

The ADEL2020AR-20 is a documented alternative within the same family, offering identical electrical characteristics but housed in a 20-lead SOIC package instead of the 8-lead PDIP configuration used by the ADEL2020AN.

FAQ

How does the disable pin affect the output impedance?

When the disable pin is pulled to common (0 V), the output becomes a high impedance state, effectively isolating the input from the output with better than 50 dB isolation at 10 MHz.

What is the recommended method for offset nulling?

A 10 kΩ potentiometer connected between Pins 1 and 5, with its wiper tied to V+, can be used to trim out the inverting input current offset.