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Product Detailed Parameters
- Description:IC CLK/FREQ SYNTH 20LFCSP
- Series:-
- Package:Tray
- Mfr:Analog Devices Inc.
- PLL:Yes
- Input:CMOS, TTL
- Output:Clock
- Number of Circuits:1
- Ratio - Input:Output:2:01
- Differential - Input:Output:Yes/No
- Frequency - Max:7.5GHz
- Divider/Multiplier:Yes/No
- Voltage - Supply:2.7V ~ 3.3V
- Operating Temperature:-40°C ~ 85°C
- Mounting Type:Surface Mount
- Package / Case:20-WFQFN Exposed Pad, CSP
- Supplier Device Package:20-LFCSP (4x4)
- Type:Clock/Frequency Synthesizer (RF)
- Grade:-
- Qualification:-
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Overview
The ADF4007BCPZ is a high-frequency divider and PLL synthesizer from Analog Devices, designed for communications applications. It operates with an RF input frequency range of 1.0 GHz to 7.5 GHz and supports a maximum phase-frequency detector (PFD) frequency of 120 MHz. The device features a precision charge pump with a typical current of 5.0 mA and accepts divide ratios of 8, 16, 32, or 64 via external control pins. Powered by a single supply between 2.7 V and 3.3 V, it includes a separate charge pump supply pin (VP) to allow extended tuning voltages up to 5.5 V. The component is housed in a 20-lead Lead Frame Chip Scale Package (CP-20-6).
Feature Summary
- Operates at RF frequencies up to 7.5 GHz with a PFD frequency limit of 120 MHz.
- Configurable N-divider prescaler supporting divide ratios of 8, 16, 32, or 64.
- Integrated low-noise digital PFD and precision charge pump with RSET-controlled current.
- Separate VP pin allows charge pump supply voltage up to 5.5 V for extended VCO tuning.
Applications
- Satellite communications systems
- Broadband wireless access networks
- CATV infrastructure equipment
- Wireless LAN implementations
Procurement Notes
Verify the specific ordering suffix when purchasing. The base part number ADF4007BCPZ indicates a tube package, while suffixes such as -RL or -RL7 denote reel packaging options. Confirm that the selected variant matches the required manufacturing quantity and handling specifications for the production line.
Selection Notes
Select the appropriate N-divider value based on the target RF output frequency and the maximum allowable PFD frequency of 120 MHz. Ensure the reference input signal meets the sensitivity requirements of 0.8 V p-p minimum. Design the external loop filter considering the charge pump current determined by the RSET resistor value to achieve the desired loop bandwidth and phase margin.
Part Context
The ADF4007BCPZ belongs to the ADF4007 family of high-frequency synthesizers. It is functionally identical to the ADF4007BCPZ-RL and ADF4007BCPZ-RL7 variants, differing only in the shipping packaging format. The 'B' designation specifies the industrial temperature range of −40°C to +85°C.
Replacement Considerations
Publicly confirmed substitute part numbers are not available in the provided documentation. Direct replacements should be evaluated based on matching RF bandwidth, PFD frequency limits, and package dimensions.
FAQ
How is the N-divider prescaler value configured?
The N-divider value is set using two external control pins, N1 and N2. Logic levels on these pins select one of four divide ratios: 8, 16, 32, or 64.
What is the purpose of the VP pin?
The VP pin provides a separate power supply for the charge pump. It allows the charge pump voltage to exceed the main AVDD/DVDD supply (up to 5.5 V), enabling the driving of VCOs with higher tuning voltage ranges in 3 V systems.
Can the ADF4007 be used as a standalone divider?
Yes, in addition to PLL synthesis, the ADF4007 can function as a high-frequency counter/divider with fixed divide ratios of 8, 16, 32, or 64.
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