— IC芯片 | 连接器 | 传感器 | 被动器件 —
Product Detailed Parameters
- Description:IC CLK/DATA REC 622MBPS 32-LFCSP
- Series:-
- PLL:Yes
- Mfr:Analog Devices Inc.
- Main Purpose:SONET/SDH
- Input:CML
- Output:LVDS
- Number of Circuits:1
- Ratio - Input:Output:1:02
- Differential - Input:Output:Yes/Yes
- Frequency - Max:622MHz
- Voltage - Supply:3V ~ 3.6V
- Operating Temperature:-40°C ~ 85°C
- Mounting Type:Surface Mount
- Package / Case:32-WFQFN Exposed Pad, CSP
- Supplier Device Package:32-LFCSP-WQ (5x5)
- Grade:-
- Qualification:-
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Overview
The ADN2804ACPZ-500RL7 is a 622 Mbps clock and data recovery (CDR) integrated circuit manufactured by Analog Devices Inc. It provides quantization, signal level detection, clock and data recovery, and data retiming for NRZ data streams without requiring an external reference clock. The device features an integrated limiting amplifier and meets SONET jitter requirements. It operates on a single 3.0 V to 3.6 V supply with typical power consumption of 423 mW. The unit is housed in a 32-lead LFCSP package.
Feature Summary
- Integrated CDR and limiting amplifier for 622 Mbps NRZ data
- Exceeds SONET OC-12 jitter transfer, generation, and tolerance specifications
- Adjustable slice level (±95 mV) and independent loss-of-signal detector
- I²C interface for accessing optional features and configuration
Applications
- SONET OC-12 systems
- BPON ONT applications
- WDM transponders
- Regenerators and repeaters
- Broadband cross-connects and routers
Procurement Notes
Verify the specific ordering suffix -500RL7 against the manufacturer's current ordering guide to confirm packaging details. Confirm that the component meets RoHS3 compliance standards as indicated in recent documentation updates. Ensure proper ESD handling procedures are followed during procurement and storage due to the sensitivity of the internal circuitry.
Selection Notes
Select this component for designs requiring standalone clock recovery at 622 Mbps without external reference clocks. Ensure the input signal is compatible with the CML differential input range. Verify that the PCB layout supports the 32-LFCSP package dimensions and thermal requirements. Consider the I²C interface availability if dynamic configuration of LOS or slice levels is required.
Part Context
This part belongs to the ADN28xx series of clock and data recovery ICs designed for optical communication interfaces. It serves as a receiver solution when paired with a PIN diode and TIA preamplifier. The ADN2804 specifically targets SONET/SDH applications at the OC-12 rate, offering a compact alternative to discrete CDR solutions.
Replacement Considerations
Public confirmed substitute part numbers are not available in the provided documentation.
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