ADN2804ACPZ

Overview

The ADN2804ACPZ is a 622 Mbps Clock and Data Recovery (CDR) IC with an integrated limiting amplifier, designed for SONET/SDH applications. It provides quantization, signal level detection, clock recovery, and data retiming for 622 Mbps NRZ data without requiring an external reference clock or programming. The device meets all SONET jitter requirements, including transfer, generation, and tolerance. It operates on a single 3.3 V supply with typical power consumption of 423 mW. Key features include adjustable slice levels, loss-of-signal detection, and an I2C interface for configuration. The component is housed in a compact 5 mm × 5 mm, 32-lead LFCSP package.

Feature Summary

• Exceeds SONET OC-12 jitter transfer, generation, and tolerance requirements
• Patented clock recovery architecture with no external reference clock required
• Adjustable slice level (±95 mV) and independent loss-of-signal detector
• I2C interface for accessing optional features and internal registers

Applications

• SONET OC-12 systems
• BPON ONT
• WDM transponders
• Regenerators/repeaters
• Broadband cross-connects and routers

Procurement Notes

Verify the specific ordering suffix and revision status directly with Analog Devices or authorized distributors, as manufacturing processes may change. Confirm RoHS compliance and moisture sensitivity levels prior to procurement. Ensure that the 32-LFCSP package dimensions and thermal characteristics align with your PCB design constraints.

Selection Notes

Select the ADN2804ACPZ for applications requiring a self-contained CDR solution for 622 Mbps NRZ signals. It is suitable when minimizing external components is critical, as it integrates the limiting amplifier. Consider the 3.3 V single-supply operation and low power dissipation for energy-efficient designs. Verify compatibility with CML input and LVDS output interfaces.

Part Context

The ADN2804 belongs to Analog Devices' family of SONET/SDH clock and data recovery ICs. It is specifically engineered for OC-12 rates, offering high sensitivity and robust jitter performance. The device simplifies receiver design by combining quantization, LOS detection, and retiming functions into a single compact package, reducing board space and component count compared to discrete solutions.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.