— IC芯片 | 连接器 | 传感器 | 被动器件 —
Product Detailed Parameters
- Description:IC CLK DATA REC SDH 1.25GHZ
- Series:-
- PLL:Yes
- Mfr:Analog Devices Inc.
- Main Purpose:SONET/SDH
- Input:CML
- Output:LVDS
- Number of Circuits:1
- Ratio - Input:Output:1:02
- Differential - Input:Output:Yes/Yes
- Frequency - Max:1.25GHz
- Voltage - Supply:3V ~ 3.6V
- Operating Temperature:-40°C ~ 85°C
- Mounting Type:Surface Mount
- Package / Case:32-WFQFN Exposed Pad, CSP
- Supplier Device Package:32-LFCSP-WQ (5x5)
- Grade:-
- Qualification:-
Download product information
Overview
The ADN2813ACPZ-RL7 is a clock and data recovery IC from Analog Devices, designed for continuous serial data rates ranging from 10 Mb/s to 1.25 Gb/s. It integrates a limiting amplifier, quantizer, and PLL-based CDR circuit. The device operates on a single 3.0 V to 3.6 V supply with a typical current consumption of 139 mA at 1.25 Gb/s. It features LVDS outputs for recovered clock and data, an I2C interface for configuration, and supports SONET/SDH jitter requirements without an external reference clock.
Feature Summary
- Integrated limiting amplifier with adjustable slice level (±95 mV) and loss-of-signal detection
- Patented delay- and phase-locked loop architecture for jitter transfer, generation, and tolerance compliance
- I2C interface for accessing optional features and internal register configuration
- Available in a compact 5 mm × 5 mm 32-lead LFCSP package
Applications
- SONET OC-1/-3/-12 and associated FEC rates
- Fibre Channel and Gigabit Ethernet (GbE)
- WDM transponders and regenerators/repeaters
- Broadband cross-connects and routers
Procurement Notes
Verify the specific ordering suffix '-RL7' against the manufacturer's official documentation to confirm reel packaging details. Confirm that the 'ACPZ' designation corresponds to the lead-free 32-LFCSP-WQ package variant. Ensure compatibility with the required 3.3 V single-supply operation and thermal management guidelines for the exposed pad.
Selection Notes
Select this component for applications requiring automatic lock to data rates between 10 Mb/s and 1.25 Gb/s without external programming. Consider the 3.3 mV typical quantizer sensitivity and the need for an external TIA preamplifier if implementing a complete fiber optic receiver. Verify that the LVDS output swing and impedance match the downstream load requirements.
Part Context
This part belongs to the ADN2813 series of clock and data recovery ICs. It is functionally similar to the ADN2812 but optimized for the 1.25 Gb/s rate. The device is often used in conjunction with PIN diodes and transimpedance amplifiers to form integrated optical receivers for high-speed serial communication systems.
Replacement Considerations
Publicly confirmed substitute part numbers are not available in the provided source material. Evaluate alternatives based on pin compatibility, data rate support up to 1.25 Gb/s, and LVDS output specifications.
ChipApex | Global Electronic Components Supplier








