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Product Detailed Parameters
- Description:IC CLOCK/DATA RECOVERY 32-LFCSP
- Series:-
- PLL:Yes
- Mfr:Analog Devices Inc.
- Main Purpose:SONET/SDH
- Input:CML
- Output:CML
- Number of Circuits:1
- Ratio - Input:Output:1:02
- Differential - Input:Output:Yes/Yes
- Frequency - Max:2.7GHz
- Voltage - Supply:3V ~ 3.6V
- Operating Temperature:-40°C ~ 85°C
- Mounting Type:Surface Mount
- Package / Case:32-WFQFN Exposed Pad, CSP
- Supplier Device Package:32-LFCSP (5x5)
- Grade:-
- Qualification:-
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Overview
The ADN2817ACPZ-RL7 is a continuous rate clock and data recovery IC from Analog Devices, designed for serial data inputs ranging from 10 Mbps to 2.7 Gbps. It features an integrated limiting amplifier with 5 mV p-p sensitivity and adjustable slice levels. The device utilizes a proprietary dual-loop architecture to automatically lock to data rates without an external reference clock or programming. It operates on a single 3.0 V to 3.6 V supply, consuming 650 mW of power. Key specifications include jitter generation of 0.046 UI p-p at OC-48 and support for double data rate modes.
Feature Summary
- Continuous rate operation from 10 Mbps to 2.7 Gbps with automatic locking
- Integrated limiting amplifier providing 5 mV p-p input sensitivity
- Proprietary dual-loop clock recovery architecture exceeding ITU-T jitter specs
- Built-in PRBS generator/detector and BER monitor capabilities
Applications
- SONET OC-1, OC-3, OC-12, OC-48, and associated FEC rates
- Fibre Channel, 2x Fibre Channel, GbE, and HDTV systems
- WDM transponders and regenerators/repeaters
- High-speed test equipment
Procurement Notes
Verify the specific suffix RL7 indicates reel packaging when sourcing. Confirm availability status as distribution channels may list limited stock or end-of-life conditions. Ensure the LFCSP-32 package dimensions match the PCB footprint requirements during procurement planning.
Selection Notes
Select this component for applications requiring high sensitivity (5 mV p-p) and adjustable slice levels via SLICEP/SLICEN pins. It is suitable for designs needing rate selectivity without a reference clock. Compare against the ADN2818 if higher input overdrive tolerance is required instead of maximum sensitivity.
Part Context
This part belongs to the ADN2817/ADN2817 family of clock and data recovery ICs. It shares the same core architecture and pinout with the ADN2818, differing primarily in input stage sensitivity and limiting amplifier configuration. The ADN2817 is optimized for lower signal amplitude inputs compared to the ADN2818.
Replacement Considerations
The ADN2818ACPZ-RL7 is a functional substitute within the same package, offering similar performance but with higher input sensitivity thresholds (200 mV p-p). Verify that the application does not require the specific 5 mV p-p sensitivity unique to the ADN2817.
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