ADN2818ACPZ

Overview

The ADN2818ACPZ is a continuous rate clock and data recovery IC designed for serial data inputs ranging from 10 Mbps to 2.7 Gbps. It operates on a single 3.0 V to 3.6 V supply, consuming a typical current of 180 mA (600 mW). The device features CML differential input and output interfaces within a 5 mm × 5 mm 32-lead LFCSP package. It automatically locks to data rates without external reference clocks or programming, exceeding ITU-T jitter specifications for SONET/SDH applications.

Feature Summary

• Continuous rate operation from 10 Mbps to 2.7 Gbps with automatic locking
• CML differential input and output interfaces
• Exceeds ITU-T jitter transfer, generation, and tolerance requirements
• Integrated Bit Error Rate Monitor (BERMON) and sample phase adjust via I²C

Applications

• SONET OC-1, OC-3, OC-12, OC-48, and associated FEC rates
• Fibre Channel, 2× Fibre Channel, GbE, and HDTV systems
• WDM transponders and regenerators/repeaters
• Test equipment requiring clock recovery

Procurement Notes

Verify the specific ADN2818 variant against the ADN2817, as the latter includes additional limiting amplifier and slice adjustment features not present in the ADN2818. Confirm that the 32-LFCSP exposed paddle is correctly connected to VEE during assembly to ensure proper thermal dissipation and electrical grounding.

Selection Notes

Select the ADN2818 when high sensitivity or adjustable slice levels are not required, as these are exclusive to the ADN2817. Ensure the design accommodates the 180 mA typical supply current and verify that the 5 mm × 5 mm LFCSP footprint matches the PCB layout guidelines provided in the datasheet.

Part Context

This component belongs to the ADN2817/ADN2818 family of clock and data recovery ICs manufactured by Analog Devices Inc. It shares the same core architecture and pinout with the ADN2817 but lacks the integrated limiting amplifier and programmable slice level controls found in the ADN2817 variant.

Replacement Considerations

The ADN2817ACPZ is a compatible alternative within the same package if higher input sensitivity (5 mV p-p) or adjustable slice levels are needed. Other ADN281x derivatives like the ADN2812 or ADN2815 offer different maximum data rates or output formats and require careful interface verification.

FAQ

Does the ADN2818 require an external reference clock?

No, the ADN2818 automatically locks to the incoming data rate without the need for an external reference clock or programming.

What is the differential input sensitivity of the ADN2818?

The differential input sensitivity is 200 mV p-p at a BER of 1 × 10⁻¹⁰ with ac-coupled PRBS 2²³−1 input.

How is the Bit Error Rate monitored?

The device includes a BERMON circuit that provides an estimate of the received bit error rate without interrupting the data, accessible via the I²C interface or an analog voltage output on the VBER pin.