ADN2917ACPZ

Overview

The ADN2917ACPZ is a continuous-rate clock and data recovery (CDR) integrated circuit manufactured by Analog Devices Inc. It supports serial data input rates from 8.5 Gbps to 11.3 Gbps without requiring an external reference clock. The device integrates limiting amplifier and equalizer inputs, providing quantization, signal level detection, and CDR functions. Key electrical parameters include a typical quantizer sensitivity of 9.2 mV p-p in limiting amplifier mode, power dissipation of 446.6 mW with the clock output enabled, and operation over a temperature range of −40°C to +85°C. It utilizes a 24-lead LFCSP package.

Feature Summary

• Supports continuous data rates from 8.5 Gbps to 11.3 Gbps
• Exceeds SONET/SDH jitter transfer, generation, and tolerance requirements
• Integrates optional limiting amplifier and adaptive/manual equalizer inputs
• Includes PRBS generator/detector and programmable LOS threshold via I²C

Applications

• SONET/SDH OC-192 systems
• 10GFC and 10GE applications with associated FECs
• XFP transceivers
• Line cards, routers, and repeaters

Procurement Notes

Verify component authenticity through authorized distributors or direct manufacturer channels. Confirm lot traceability and check for EOL status notifications, as discontinuance notices may apply. Ensure storage conditions comply with moisture sensitivity levels specified in the datasheet prior to soldering.

Selection Notes

Select this component for high-speed optical interconnects requiring robust jitter performance exceeding standard SONET/SDH masks. Consider the integrated limiting amplifier for high-sensitivity applications or the equalizer mode for long-reach transmission lines. Verify that the system design accommodates the required 1.2 V, 1.8 V to 3.3 V, and 3.3 V power supplies.

Part Context

This part belongs to the ADN2917 series of clock and data recovery ICs designed for high-speed serial communication. It is functionally similar to other members of the family but specifically optimized for the 8.5 Gbps to 11.3 Gbps rate range. The device shares packaging and interface characteristics with related models like the ADN2913 and ADN2915.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Evaluate cross-reference options based on pin compatibility and electrical specifications only if official substitution lists are published by the manufacturer.

FAQ

Does the ADN2917 require an external reference clock?

No, the ADN2917 automatically locks to data signals without the need for an external reference clock or programming, though an optional reference clock input is available.

What is the typical quantizer sensitivity in limiting amplifier mode?

The typical quantizer sensitivity is 9.2 mV p-p when operating in limiting amplifier mode at OC-192 rates.

How is the Loss of Signal (LOS) detected?

The receiver front-end includes an LOS detector circuit that indicates when the input signal level falls below a user-programmable threshold, featuring hysteresis to prevent output chatter.