ADSP-21160MKBZ-80

Digital Signal Processor Dsp Overview

The ADSP-21160MKBZ-80 is a high-performance 32-bit floating-point digital signal processor from the SHARC family, fabricated using a 0.25 micron CMOS process. It operates at a core instruction rate of 80 MHz with a 12.5 ns cycle time. The device features a Single-Instruction Multiple-Data (SIMD) architecture containing two computational processing elements (PEX and PEY), each equipped with an ALU, multiplier, shifter, and register file. It integrates 4 Mbits of dual-ported on-chip SRAM, an I/O processor supporting 14 DMA channels, and multiple interfaces including six link ports, two serial ports, and a host interface. The component is housed in a 400-ball 27 mm × 27 mm PBGA package.

Digital Signal Processor Dsp Feature Summary

• SIMD Architecture: Two parallel computational units (PEX/PEY) enable double performance for math-intensive algorithms compared to single-unit predecessors.
• Integrated Memory: 4 Mbits of dual-ported on-chip SRAM allows independent access by the core and I/O processor without wait states.
• Multiprocessing Support: Glueless connection for up to six processors via distributed bus arbitration and six dedicated link ports.
• High-Speed Interfaces: Includes two synchronous serial ports, six link ports, and a 64-bit external port for asynchronous/synchronous memory interfacing.

Digital Signal Processor Dsp Applications

• Audio processing and decoding
• Medical imaging systems
• Military signal processing
• Graphics and video imaging
• Communication equipment

Digital Signal Processor Dsp Procurement Notes

Verify the specific ordering suffix KBZ-80 against the manufacturer's current ordering guide to confirm package type and temperature range availability. Check for product change notifications regarding the 0.25 micron process node status. Ensure compatibility with development tools such as CrossCore Embedded Studio or VisualDSP++ for code migration from ADSP-2106x families.

Digital Signal Processor Dsp Selection Notes

Select the ADSP-21160M over the ADSP-21160N when lower power consumption at 100 MHz is not required, as the M variant uses a 0.25 micron process versus the N's 0.18 micron process. Confirm that the 80 MHz instruction rate meets the system timing requirements. Verify assembly source code compatibility if migrating from ADSP-2106x designs, noting that SIMD optimization requires code modifications.

Digital Signal Processor Dsp Part Context

The ADSP-21160M is part of the ADSP-21160x SHARC DSP family, which also includes the higher-performance ADSP-21160N. This family bridges the gap between the first-generation ADSP-2106x and newer SHARC cores, offering backward assembly compatibility while introducing SIMD capabilities. It represents a significant evolution in the SHARC line by integrating multiprocessing features directly onto the die.

Digital Signal Processor Dsp Replacement Considerations

The ADSP-21160N is the direct performance upgrade within the same package and pinout, offering 100 MHz operation and lower power via a 0.18 micron process. For legacy replacements, the ADSP-21060 series is assembly-compatible but lacks SIMD hardware and integrated multiprocessing features.