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ADSP-21587KBCZ-4B is listed in the Digital Signal Processor Dsp range at ChipApex. The manufacturer field lists Analog Devices Inc.. Its product description is 2XSHARC DUALDDR,HPCP. Review the specifications below when checking this part for your BOM.
The ADSP-21587KBCZ-4B is a dual-core SHARC+ digital signal processor from Analog Devices, housed in a 19 mm × 19 mm 349-ball BGA package. It features two SHARC+ cores operating at up to 500 MHz, each with 640 kB of Level 1 SRAM. The device supports 32-bit, 40-bit, and 64-bit floating-point operations alongside 32-bit fixed-point processing. Key system components include an Arm Cortex-A5 core running at 500 MHz, 256 kB of shared L2 SRAM with ECC protection, and a 512 kB L2 ROM. Peripheral interfaces include DDR3/DDR2/LPDDR1 controllers, USB 2.0 HS, PCIe 2.0, and multiple audio interfaces.
Verify the specific ordering suffix against the manufacturer's current datasheet to confirm package type and temperature range. Ensure compatibility with required external memory interfaces such as DDR3 or LPDDR1. Confirm that the 349-ball BGA footprint matches the target PCB design constraints.
Select this component for applications requiring high-performance floating-point DSP capabilities combined with general-purpose computing via the Arm Cortex-A5. Consider the 500 MHz maximum frequency and 640 kB L1 SRAM per core for algorithm complexity. Verify peripheral requirements against the available USB, PCIe, and audio interfaces provided in the 349-ball package.
This part belongs to the ADSP-SC58x/ADSP-2158x family, which integrates SHARC+ DSP cores with an Arm Cortex-A5 processor. The ADSP-21587 variant specifically targets high-performance applications without the specific automotive qualification suffixes found in other family members like the SC587W.
Direct replacements within the same package and feature set include the ADSP-SC587 series for automotive-grade variants or the ADSP-21584 for similar performance levels. Cross-model selection requires verifying pin compatibility and memory configurations.
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