AFS090-1FG256

Overview

The AFS090-1FG256 is a Fusion mixed-signal FPGA featuring 38,400 configurable logic blocks and 1.5 million system gates in a 256-pin Fine Pitch Ball Grid Array package. It utilizes an advanced 130-nm flash-based CMOS process for nonvolatile configuration. The device integrates up to 8 Mbits of user flash memory, a 12-bit ADC with up to 30 scalable analog input channels, and multiple clock conditioning circuits. Operating on a single 3.3 V supply with an internal 1.5 V regulator, it supports industrial temperature ranges and provides secure in-system programming via AES encryption.

Feature Summary

• Integrates high-performance flash-based FPGA fabric with embedded analog peripherals including a 12-bit ADC and MOSFET gate drivers.
• Provides instant-on operation without external boot PROMs, retaining programmed designs when powered off.
• Supports secure in-system programming and IP protection using 128-bit AES encryption and FlashLock technology.
• Features versatile I/O banks supporting mixed-voltage standards from 1.5 V to 3.3 V with hot-swappable capabilities.

Applications

• Power management systems and smart battery charging controllers
• Clock generation and distribution networks
• Motor control applications requiring integrated analog sensing

Procurement Notes

Verify the specific ordering suffix against the manufacturer's current product status table. Confirm that the required speed grade and temperature range match the design specifications. Ensure the selected package variant aligns with the pinout requirements for the target PCB layout. Check for any updates regarding RoHS compliance or lead-free packaging options before finalizing the purchase order.

Selection Notes

Select this component based on the requirement for 38,400 CLBs and 1.5 million system gates within a 256-pin FBGA package. Evaluate the need for the integrated 12-bit ADC and analog I/O capabilities versus discrete solutions. Consider the power consumption characteristics and the benefit of single-supply operation. Verify compatibility with the Libero SoC development tools for configuration and analog peripheral setup.

Part Context

This part belongs to the Microsemi Fusion family of mixed-signal FPGAs, which combines programmable logic with embedded analog functions. It shares architectural similarities with other Fusion devices like the AFS250 and AFS600 but offers a specific density of 38,400 tiles. The family is characterized by its flash-based nonvolatile technology and integration of ADCs and gate drivers.

Replacement Considerations

Direct pin-compatible replacements within the same package are limited to other Fusion devices with similar I/O counts. Cross-family migration to ProASIC3 or SmartFusion may require schematic redesign due to differences in analog integration and pin assignments.

FAQ

Does the AFS090-1FG256 require an external configuration PROM?

No, the device uses flash-based technology that retains configuration data when powered off, enabling instant-on operation without external boot PROMs.

What is the maximum resolution of the integrated ADC?

The integrated Analog-to-Digital Converter supports up to 12-bit resolution with a cumulative sample rate of up to 600 Ksps.

How is intellectual property protected in this device?

IP is protected using FlashLock technology and 128-bit AES encryption, which secures both the configuration data and the embedded flash memory blocks.