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The AFS090-2FGG256 is a Fusion mixed-signal FPGA featuring 90,000 system gates and 2,304 tiles. It utilizes an advanced 130-nm flash-based CMOS process with seven metal layers. The device includes 2 Mbits of embedded user flash memory and 1 Kbit of FlashROM. It supports up to 75 digital I/Os across four banks and integrates five analog quads providing 15 input channels and five gate driver outputs. The integrated ADC offers up to 12-bit resolution at 600 Ksps. Operating from a single 3.3 V supply, it delivers 350 MHz system performance in the -2 speed grade within the FG256 package.
Verify the specific ordering suffix against the manufacturer's current datasheet to confirm package type, temperature range, and security licensing status. Ensure compatibility with Libero SoC software versions supporting the Fusion family. Confirm RoHS compliance requirements if applicable to the target assembly process.
Select this component when a low-gate-count solution requires integrated analog capabilities without discrete components. The -2 speed grade provides higher frequency performance than standard variants. Verify that the 2 Mbit flash capacity meets storage needs for configuration and data logging tasks.
This part belongs to the Microsemi Fusion family of mixed-signal FPGAs. It shares architectural features with the AFS250, AFS600, and AFS1500 devices but offers lower logic density. The FG256 package provides a fine-pitch ball grid array form factor suitable for compact board layouts.
Pin-compatible alternatives within the same package include other AFS090 variants with different speed grades or temperature ratings. Cross-family migration to ProASIC3 devices may require significant schematic and code modifications due to architectural differences.