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The AGL030V5-QNG48 is an IGLOO flash FPGA from Microchip Technology, utilizing a 130-nm process. It provides 30,000 system gates and 768 VersaTiles (D-flip-flops). The device operates with a core voltage range of 1.2V to 1.5V and supports up to 49 user I/Os in the QN48 package. It features Flash*Freeze technology for ultra-low power retention and includes 1 kbit of nonvolatile FlashROM. The component lacks embedded SRAM and integrated PLLs.
Verify the ordering suffix 'V5' indicates the specific voltage grade and packaging variant required for your design. Confirm that the QN48 package dimensions align with your PCB footprint constraints. Ensure the commercial temperature range meets your operational environment specifications before finalizing procurement.
Select this model if your design requires approximately 30,000 system gates and fits within the 49 I/O limit of the QN48 package. Note that this specific device does not include embedded RAM or a PLL; designs requiring these features must utilize higher-density IGLOO models such as the AGL060 or above.
This part belongs to the IGLOO family of low-power flash FPGAs. It is architecturally compatible with other devices in the series but offers lower density compared to models like the AGL060 or AGL125. The V5 suffix denotes the specific voltage support and manufacturing revision within the product line.
For pin-compatible upgrades, consider the AGL060V5-QNG48 which adds RAM and PLL capabilities. For downward migration, the AGL015 is available but is not recommended for new designs. Verify logic resource sufficiency when substituting with lower-density parts.
No, the AGL030 device does not support embedded SRAM. Users requiring memory resources should select a higher-density device such as the AGL060.
The QN48 package supports up to 49 single-ended user I/Os. This count may be reduced if differential I/O pairs are utilized or if the Flash*Freeze pin is used as a dedicated control signal.
No, the AGL030 device does not include an integrated Phase-Locked Loop (PLL). Clock conditioning must be handled externally or through simpler clock conditioning circuits if supported by the specific package variant.