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The AGL060V2-CSG121 is a Field Programmable Gate Array from the Microsemi IGLOO family, utilizing a 130-nm flash-based CMOS process. It provides 60,000 system gates and 1,536 VersaTiles (D-flip-flops). The device features 18 kbits of true dual-port SRAM organized into four 4,608-bit blocks and includes 1 kbit of FlashROM user nonvolatile memory. It operates with a core voltage range of 1.2 V to 1.5 V and supports mixed-voltage I/O standards including LVCMOS and LVTTL. The component is housed in a CS121 Chip Scale Package with 96 user I/Os and a 0.5 mm pitch.
Verify the specific ordering suffix to confirm the package type and temperature grade. Ensure the design toolchain supports the IGLOO V2 architecture and the 130-nm process node. Confirm that the selected package variant meets the mechanical footprint requirements for the target PCB layout.
Select this device when designs require moderate logic density with significant emphasis on power efficiency and security. The V2 suffix indicates support for a wider core voltage range compared to V5 variants. Verify that the required number of I/O banks and RAM blocks aligns with the specific capacity limits of the AGL060 density tier.
This component belongs to the IGLOO Low Power Flash FPGA family, which bridges the gap between ASIC costs and FPGA flexibility. It is designed for applications demanding small form factors and high reliability. The family utilizes nonvolatile flash technology to eliminate configuration overhead and provide firm-error immunity against radiation-induced soft errors.
Check for pin-compatible packages within the same density tier, such as FG144 or QN132, if different mounting styles are required. Higher density devices like AGL125 may offer additional resources but require verification of thermal and power constraints.