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The AGL060V5-CS121 is a Microsemi IGLOO Low Power Flash FPGA featuring 60,000 system gates and 1,536 VersaTiles. It utilizes a 130-nm flash process with 18 kbits of dual-port SRAM and 1 kbit of FlashROM. The device operates on a 1.2 V to 1.5 V core voltage and supports mixed-voltage I/O standards including LVCMOS 1.2 V/1.5 V/1.8 V/2.5 V/3.3 V. It includes six Clock Conditioning Circuits (CCC) but lacks an integrated PLL in the CS121 package. The component offers 96 user I/Os in a 6 mm x 6 mm Chip Scale Package (CSP) with 0.5 mm pitch.
Verify the specific ordering suffix against the manufacturer's current datasheet revision to confirm temperature grade and packaging compliance. Ensure the design flow supports the 130-nm process node and verify that the CS121 package pinout matches the target PCB footprint constraints.
Select this model when 60,000 system gates are sufficient for the logic density requirements. The CS121 package is suitable for space-constrained designs needing a small footprint. Note that this specific package variant does not support the integrated Phase-Locked Loop (PLL) feature found in other packages within the same device family.
This component belongs to the IGLOO V5 series of low-power flash FPGAs from Microsemi. It represents a mid-range density option within the family, offering a balance between logic capacity and power efficiency. The V5 designation indicates specific process and feature enhancements over earlier generations.
Check for AGL060V2 variants if the application requires different voltage ranges or legacy compatibility. Verify pin compatibility across the IGLOO family if migrating to higher gate counts like the AGL125.