SEARCH
— IC芯片 | 连接器 | 传感器 | 被动器件 —
The AGL060V5-CSG121I is a flash-based Field Programmable Gate Array (FPGA) from the IGLOO V5 family, manufactured by Microsemi. It features 60,000 system gates and 1,536 VersaTiles (D-flip-flops). The device operates with a core voltage range of 1.2 V to 1.5 V and supports single-voltage system operation. It includes 18 kbits of RAM organized in four 4,608-bit blocks and 1 kbit of FlashROM user nonvolatile memory. The part is housed in a CS121 Chip Scale Package with 121 pins, measuring 6 mm x 6 mm. It supports up to 96 user I/Os and offers mixed-voltage operation for 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V standards. The industrial temperature grade (-40°C to +100°C junction temperature) is indicated by the 'I' suffix.
Verify the specific ordering suffix 'I' confirms the industrial temperature range (-40°C to +100°C junction temperature) required for your application environment. Confirm that the CS121 package dimensions and pinout match your PCB footprint design constraints. Ensure the design tool version supports the IGLOO V5 architecture and Flash*Freeze features.
Select this device if the design requires approximately 60,000 system gates and fits within the 121-pin constraint of the CS121 package. Consider the AGL060V5 series for its balance of logic density and low power consumption. Verify that the required I/O standards are compatible with the supported voltage levels (1.2 V to 3.3 V). Check if the absence of an integrated PLL in the CS121 package variant meets the clocking requirements.
This component belongs to the IGLOO Low Power Flash FPGA family, which utilizes a 130-nm flash process. The IGLOO family is characterized by its nonvolatile nature, low power modes, and security features. The AGL060 variant sits in the mid-range of the family, offering 60,000 gates compared to lower-density parts like the AGL030 or higher-density parts like the AGL250.
Pin-compatible packages within the IGLOO family include other densities such as AGL125 or AGL250 in similar footprints, though I/O counts may vary. For migration, consult the IGLOO FPGA Fabric User Guide to ensure compliance with design and board migration requirements between different gate counts and package types.