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The AGL125V5-VQ100I is a flash-based Field Programmable Gate Array (FPGA) from the IGLOO family, manufactured by Microchip Technology. It features 125,000 system gates and 3,072 VersaTiles. The device operates with a core voltage range of 1.425 V to 1.575 V and supports up to 133 user I/Os in a VQFP-100 package. It includes 36 kbits of SRAM and 1 kbit of FlashROM. The component supports industrial temperature ranges (-40°C to +100°C junction temperature), offers Flash*Freeze technology for ultra-low power retention, and provides AES-protected In-System Programming capabilities.
Verify the specific ordering suffix 'V5' indicates a 1.5V-only core voltage variant, distinct from the 'V2' series which supports 1.2V operation. Confirm the 'I' suffix corresponds to the industrial temperature grade (-40°C to +100°C). Ensure compatibility with the VQFP-100 package dimensions and pitch specifications during board layout planning.
Select this device when 125,000 system gates are required within a compact VQFP-100 footprint. It is suitable for designs prioritizing nonvolatile configuration and low power over the highest possible clock frequencies found in larger density devices. Verify that the 1.5V core voltage requirement aligns with the system power supply constraints.
This component belongs to the IGLOO Low Power Flash FPGA family, characterized by its 130-nm process technology and single-chip solution architecture. It serves as a mid-density option within the series, bridging lower-end models like the AGL060 and higher-capacity variants such as the AGL250.
For pin-compatible upgrades or downgrades within the same package, consider the AGL060 or AGL250 series. Note that the AGL250 offers double the logic resources but may require verification of power and thermal characteristics compared to the AGL125.
No, standard IGLOO devices do not support embedded processors. Devices supporting the ARM Cortex-M1 soft processor have part numbers beginning with M1AGL.
The Industrial temperature grade (-I suffix) supports a maximum junction temperature of +100°C.
When Flash*Freeze mode is activated via the dedicated pin, the device automatically shuts off clocks and inputs to the FPGA core. If the Flash*Freeze pin is used as a regular I/O, the count of available single-ended user I/Os is reduced by one.