AGL400V2-FG484

Overview

The AGL400V2-FG484 is a Field Programmable Gate Array from the IGLOO family, manufactured by Microsemi Corporation. It features 400,000 system gates and 9,216 VersaTiles (D-flip-flops). The device operates with a core voltage range of 1.2 V to 1.5 V and supports up to 194 user I/Os in the FG484 package. It includes 54 kbits of RAM organized into twelve 4,608-bit blocks, one integrated PLL within the Clock Conditioning Circuits, and 1 kbit of FlashROM. The component utilizes a 130-nm flash-based CMOS process.

Feature Summary

• Flash*Freeze technology enables ultra-low power consumption while retaining FPGA content without requiring external components.
• Instant On Level 0 support allows immediate operation upon power-up without an external boot PROM.
• Integrated AES decryption engine provides secure In-System Programming via JTAG.
• Nonvolatile flash architecture ensures immunity to firm errors caused by high-energy neutrons.

Applications

• Portable electronics requiring low static and dynamic power consumption
• Systems needing secure remote field updates over public networks
• Applications requiring instant-on functionality for critical task initialization

Procurement Notes

Verify that the ordering suffix matches the required temperature grade and packaging specifications. Confirm whether the design requires the Cryptography Research, Inc. patent license, indicated by the 'Y' suffix. Ensure the selected variant aligns with the specific core voltage requirements of the target system.

Selection Notes

Select this model for designs requiring 400,000 system gates with a fine-pitch ball grid array package. Consider the AGL400V2 variant for flexibility between 1.2 V and 1.5 V core voltages to optimize power efficiency. Verify pin compatibility if migrating from other devices in the IGLOO family.

Part Context

This component belongs to the IGLOO Low Power Flash FPGAs family, which is based on a 130-nm process. The family ranges from 15,000 to 1,000,000 system gates. The AGL400 represents a mid-range density option within this series, offering a balance of logic capacity and I/O availability.

Replacement Considerations

Devices such as AGL400V5-FGG484 are available in the same package footprint. Note that V5 devices carry specific marking distinctions compared to V2 devices. Verify functional equivalence regarding I/O standards and memory resources before substitution.

FAQ

Does the AGL400V2 support AES decryption?

Yes, the AGL400 device includes an on-chip 128-bit Advanced Encryption Standard decryption engine for secure In-System Programming.

What is the maximum number of user I/Os available in the FG484 package?

The AGL400 device supports up to 194 single-ended user I/Os when configured in the FG484 package.

How does Flash*Freeze mode affect I/O states?

During Flash*Freeze mode, I/O states are tristated or can be set to a specific state using weak pull-up or pull-down configurations, while consuming minimal power.