ARRIA 10 GT

Overview

The Intel Arria 10 GT is a Field Programmable Gate Array (FPGA) from the Arria 10 family, designed for high-performance data center and infrastructure applications. It features up to 78 full-duplex transceivers capable of chip-to-chip data rates up to 25.78 Gbps. The device supports extended temperature grades (-E1, -E2, -E3) with specific power supply requirements, including VCCIO operating at 1.2V to 3.0V and transceiver supplies VCCT_GXB/VCCR_GXB ranging from 0.92V to 1.14V depending on speed grade. It includes hardened PCIe Gen1/Gen2/Gen3 IP and supports dynamic partial reconfiguration.

Feature Summary

• Up to 78 full-duplex transceivers with data rates up to 25.78 Gbps chip-to-chip
• Hardened PCI Express* protocol stack supporting Gen1, Gen2, and Gen3 speeds
• Supports dynamic and partial reconfiguration for system flexibility
• Available in extended temperature grades (-E1, -E2, -E3) with low-power options

Applications

• Data center acceleration and infrastructure processing
• High-speed serial communication interfaces
• PCI Express endpoint and root port implementations

Procurement Notes

Verify the specific speed grade suffix (e.g., -E1, -E2, -E3) and power option suffix (L, S, V, H) required for the design's performance and thermal constraints. Confirm package availability and pinout compatibility during procurement planning. Ensure power sequencing adheres to AN 692 guidelines for reliable operation.

Selection Notes

Select the appropriate speed grade based on timing closure requirements; -E1 offers the fastest performance while -E3 may offer lower cost or power trade-offs. Choose power suffixes (L for low static power, V for reduced voltage operation) according to power budget constraints. Verify that the chosen VCCIO and transceiver supply voltages match the target I/O standards and data rates.

Part Context

The Arria 10 GT variant is part of the broader Arria 10 FPGA family, which also includes GX and SX devices. While GX devices support up to 17.4 Gbps and SX devices include a Hard Processor System (HPS), the GT variant focuses on maximizing transceiver count and speed for pure FPGA logic applications without an integrated ARM processor core.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Designers should consult Intel's migration guides for potential transitions to Agilex families if future-proofing is required.