AS1160-BCCT

Overview

The AS1160-BCCT is a serializer and the AS1161 is its corresponding deserializer, forming a Bus LVDS interface pair. The AS1160 converts 10-bit parallel LVCMOS/LVTTL data into a single high-speed serial LVDS stream with an embedded clock, supporting frequencies from 20MHz to 66MHz (up to 660 Mbps). The AS1161 reverses this process, recovering parallel data and clock from the serial input. Both devices operate on a 3.0V to 3.6V supply, consume less than 500mW as a chipset at 66MHz, and feature IEEE 1149.1 JTAG compliance for boundary scan testing.

Feature Summary

• Serializes 10-bit parallel data into a single differential LVDS pair to eliminate multi-channel skew.
• Includes IEEE 1149.1 JTAG test access port with at-speed BIST mode for interconnect verification.
• Features powerdown mode to reduce supply current during idle periods.
• Provides high impedance on receiver inputs during power-off conditions.

Applications

• Cellular phone base stations
• Add-drop muxes and digital cross-connects
• DSLAMs, network switches, and routers
• Backplane interconnect systems

Procurement Notes

Verify the specific suffix 'BCCT' against the manufacturer's official ordering information to confirm package type, temperature range, and reel specifications. Ensure the component source matches the original manufacturer or authorized distributor to guarantee authenticity and datasheet compliance.

Selection Notes

Select the AS1160 for transmitting parallel data to serial LVDS and the AS1161 for receiving it. Ensure the system clock frequency falls within the 20MHz to 66MHz range. Verify that the PCB layout supports the CTBGA 49-bumps package and that power supplies are decoupled as specified in the electrical characteristics.

Part Context

This component belongs to the AS1160/AS1161 series of Bus LVDS serializers and deserializers manufactured by ams-OSRAM USA INC. (formerly austriamicrosystems). These devices are designed for high-speed data transmission where reduced trace count and cost efficiency are critical.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Consult the manufacturer for direct replacements or compatible alternatives within the same product family.

FAQ

How does the device handle synchronization?

Assertion of SYNC1 or SYNC2 pins for at least five clock cycles transmits a synchronization signal (SYNCPAT) on the serial output to align the deserializer.

What is the function of the PWDNN pin?

Driving the PWDNN pin low shuts down the PLL, tri-states the outputs, and places the device into a low-power sleep mode.

Can the devices be tested at speed?

Yes, both devices support an at-speed Built-In Self-Test (BIST) mode via the IEEE 1149.1 JTAG interface to verify interconnects.