AS6501-FLQM

Overview

The AS6501-FLQM is a high-performance, two-channel time-to-digital converter (TDC) frontend device manufactured by ScioSense. It features LVDS stop inputs and serial outputs for each channel. The device supports a maximum data throughput of 70 MSPS per stop input when channels are combined, or 35 MSPS per channel independently. Single-shot accuracy ranges from 10 ps rms to 20 ps rms depending on the resolution setting. It operates with a supply voltage between 2.4 V and 3.6 V and functions within a temperature range of -40°C to +125°C.

Feature Summary

• Supports independent dual-channel operation or combined single-channel mode for higher throughput.
• Features automatic calibration to the reference clock without requiring external PLL or DLL circuits.
• Includes integrated linear voltage regulators and 16-stage FIFO buffers per channel.
• Provides configurable high-resolution modes to optimize measurement precision.

Applications

• Automated test equipment
• Laser range measurement
• Medical imaging
• Time-of-flight measurement
• Particle physics

Procurement Notes

Verify the specific ordering code AS6501-FLQM against official ScioSense documentation to confirm package type and delivery form. Ensure that interface requirements such as LVDS signaling and SPI configuration align with system design specifications before procurement.

Selection Notes

Select this component for applications requiring high-speed time measurements with precise synchronization. Consider the power dissipation limits and thermal management requirements when operating at maximum conversion rates. Verify compatibility with the host system's reference clock frequency and input signal levels.

Part Context

This part belongs to the AS6501 series of time-to-digital converters. It is designed for high-precision timing applications where low jitter and high throughput are critical. The FLQM suffix indicates the QFP48 package variant delivered in tape and reel format.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Consult ScioSense technical support for potential alternatives if this specific package or variant is unavailable.

FAQ

What is the maximum pulse-to-pulse spacing for the AS6501?

The minimum pulse-to-pulse spacing varies based on the resolution setting: 20 ns in standard mode, 50 ns in 2x resolution mode, and 100 ns in 4x resolution mode.

How does the AS6501 handle calibration?

The device performs automatic calibration to the applied reference clock, eliminating the need for external Phase-Locked Loops (PLL) or Delay-Locked Loops (DLL).

What is the function of the CHANNEL_COMBINE register bit?

Setting this bit combines the two stop channels into one, allowing for improved pulse pair resolution or a higher maximum conversion rate of up to 70 MSPS.