AT17C002A-10JI

Overview

The AT17C002A-10JI is a 2-Mbit serial EEPROM configurator designed for Altera FLEX devices. It operates at 5V with an industrial temperature range of -40°C to +85°C. The device is housed in a 20-lead Plastic J-leaded Chip Carrier (PLCC) package. Key electrical characteristics include a maximum input clock frequency of 12.5 MHz in slave mode and standby current of 500 µA. It features an internal oscillator, programmable reset polarity, and a system-friendly READY pin.

Feature Summary

• Stores configuration programs for Field Programmable Gate Arrays using a simple serial-access procedure.
• Supports cascading multiple devices via nCASC handshaking for higher-density configurations.
• Allows user-programmable OE pin polarity for flexible reset function integration.
• Includes an open-collector READY pin to indicate power-on reset completion status.

Applications

• Configuration of Altera FLEX FPGA devices
• In-system programming via 2-wire bus interface
• Cascaded memory arrays for expanded configuration capacity

Procurement Notes

Verify the specific ordering suffix 'JI' confirms the Industrial temperature grade (-40°C to +85°C) and 5V supply requirement. Confirm the 20-lead PLCC package matches the target PCB footprint. Ensure compatibility with the intended FPGA protocol before procurement.

Selection Notes

Select this part for applications requiring direct interfacing with Altera FLEX devices without external controllers. Choose the 5V version over the LV variant if the system operates at nominal 5V. Consider the PLCC package constraints versus TQFP options based on board space requirements.

Part Context

This component belongs to the AT17A Series of FPGA Configuration EEPROMs manufactured by Atmel, now part of Microchip Technology. It serves as a dedicated memory solution for loading configuration data into SRAM-based FPGAs, replacing older parallel configuration methods with a simplified serial interface.

Replacement Considerations

The datasheet identifies the AT17C/LV002A series as replacements for Altera EPC2 devices. Verify that any substitute maintains the 2-Mbit density and compatible serial protocol for the target FPGA.

FAQ

How does the device handle cascading?

Multiple devices can be linked using the nCASC output pin, which drives the nCS input of the subsequent device low when the address counter reaches its maximum value.

What is the function of the READY pin?

The READY pin is an open-collector indicator driven low during the power-on reset cycle and tri-stated when the cycle is complete, signaling readiness for configuration.