AT17C010-10JC

Overview

The AT17C010-10JC is a 1-Mbit (1,048,576 x 1-bit) serial configuration EEPROM designed for Field Programmable Gate Arrays. It operates at a nominal 5V supply voltage and supports In-System Programming via a 2-wire bus. The device features a simple serial interface compatible with FPGA master modes, offering programmable reset polarity and a system-friendly READY pin to indicate valid power levels during startup.

Feature Summary

• EE Programmable Serial Memory
• In-System Programmable via 2-wire Bus
• Programmable Reset Polarity
• System-friendly READY Pin

Applications

• Configuration of Xilinx XC3000, XC4000, XC5200, Spartan, and Virtex FPGAs
• Configuration of Altera FLEX and APEX Devices
• Configuration of Atmel AT6000, AT40K, and AT94K Devices
• Configuration of Lucent ORCA FPGAs

Procurement Notes

Verify the specific suffix 'JC' corresponds to the 20-lead PLCC package and commercial temperature range as defined in the ordering information table. Confirm that the 5V operation requirement aligns with your system design, as this part is distinct from the LV series. Ensure compatibility with standard programmers or ISP cables for initial programming needs.

Selection Notes

Select this component when a 1-Mbit capacity is required for FPGA configuration. Choose the AT17C010-10JC over the LV variant if the system operates strictly at 5V. Consider the 20-lead PLCC package for board layout requirements. Verify that the target FPGA supports Master Serial Mode for direct interfacing without an external controller.

Part Context

This device belongs to the AT17 Series of FPGA Configuration EEPROMs, which also includes the 512-Kbit AT17C512. The series provides cost-effective configuration memory solutions. The AT17C010-10JC is the high-density version within the 5V commercial grade lineup, sharing pinouts and functional characteristics with other members of the family while offering double the storage capacity.

Replacement Considerations

AT17LV010-10JC

FAQ

How does the READY pin function during power-up?

The READY pin is an open-collector output that is driven Low during the power-on reset cycle and released (tri-stated) when the power-up is complete, signaling a good power level to the FPGA.

Can multiple AT17C010-10JC devices be used together?

Yes, the devices are cascadable. The CEO output of one device connects to the CE input of the next, allowing support for additional configurations or higher-density arrays.

Is the reset polarity fixed?

No, the reset polarity is programmable. Users can select the logic polarity of the reset function by programming four specific EEPROM bytes.