AT17LV002-10SU

Overview

The AT17LV002-10SU is a 2-Mbit (2,097,152 x 1-bit) serial EEPROM designed for FPGA configuration. It operates within a supply voltage range of 3.0V to 3.6V or 4.5V to 5.5V and supports an industrial temperature range of -40°C to +85°C. The device utilizes a simple serial interface compatible with SRAM-based FPGAs in Master Serial mode. It features In-System Programmability via a 2-wire bus and includes cascading capabilities through the CEO output pin.

Feature Summary

• Supports both 3.3V and 5.0V system applications
• Enables In-System Programming via a 2-wire serial bus
• Provides cascading read-back functionality for multi-device configurations
• Allows programmable reset polarity selection

Applications

• Configuration memory for Xilinx XC3000, XC4000, and Spartan FPGAs
• Configuration memory for Altera FLEX and APEX devices
• Configuration memory for Atmel AT6000, AT40K, and AT94K devices
• Cascaded configuration arrays for high-density FPGA systems

Procurement Notes

Verify that the ordering suffix 'SU' corresponds specifically to the 20-lead SOIC package option as defined in the manufacturer's ordering guide. Confirm the component meets the required industrial temperature specifications (-40°C to +85°C). Ensure compatibility with the target FPGA's master serial mode requirements before procurement.

Selection Notes

Select this component when a 2-Mbit capacity is required for FPGA configuration. The 20-lead SOIC package is suitable for surface-mount assembly where space constraints differ from PLCC or TQFP options. Verify that the design supports the specific pinout differences between the 20-lead SOIC and other package types within the AT17LV family.

Part Context

This part belongs to the AT17LV series of FPGA Configuration EEPROMs manufactured by Microchip Technology (formerly Atmel). The series provides non-volatile storage for programming bitstreams into Field Programmable Gate Arrays. The AT17LV002 represents the 2-Mbit density tier within this product line.

Replacement Considerations

AT17LV002-10JU (20-lead PLCC)

FAQ

Is the AT17LV002-10SU compatible with Xilinx Virtex FPGAs?

No, the datasheet specifies compatibility with Xilinx XC3000, XC4000, and XC5200 families, but does not list Virtex devices.

What is the function of the CEO pin on the AT17LV002?

The CEO (Chip Enable Output) pin goes Low when the address counter reaches its maximum value, allowing it to drive the CE input of the next configurator in a daisy-chain sequence.