AT17LV128-10JC

Configuration PROMs For FPGAs Overview

The AT17LV128-10JC is a 131,072-bit serial EEPROM configured as FPGA configuration memory. It operates within a 4.75V to 5.25V supply range and supports a maximum clock frequency of 10 MHz with a 75 ns access time. The device utilizes a 20-lead Plastic Leaded Chip Carrier (PLCC) package. It features In-System Programmability via a Two-Wire Bus and includes programmable reset polarity.

Configuration PROMs For FPGAs Feature Summary

• Designed specifically for storing configuration programs for Field Programmable Gate Arrays
• Supports In-System Programming through a Two-Wire Serial Bus interface
• Features cascading capability via Chip Enable Output for multi-device configurations
• Allows user-programmable logic polarity for the reset function

Configuration PROMs For FPGAs Applications

• Configuration of Xilinx XC3000, XC4000, and Spartan FPGAs
• Configuration of Altera FLEX and APEX devices
• Configuration of Atmel AT6000, AT40K, and AT94K devices
• Configuration of Lucent ORCA FPGAs

Configuration PROMs For FPGAs Procurement Notes

Verify that the component matches the specific 20-lead PLCC package designation. Confirm the voltage rating aligns with the required 5.0V application parameters. Ensure the industrial or commercial temperature grade meets system requirements. Check for lead-free compliance if environmental regulations apply to the design.

Configuration PROMs For FPGAs Selection Notes

Select this part when a 128-Kbit capacity is required for FPGA initialization. The 20-lead PLCC form factor suits designs utilizing legacy surface-mount footprints. Verify compatibility with the target FPGA's master serial mode timing constraints. Consider the low-power standby mode benefits for battery-operated systems.

Configuration PROMs For FPGAs Part Context

This component belongs to the AT17LV series of serial EEPROM configurators manufactured by Microchip Technology. The series provides cost-effective memory solutions for SRAM-based FPGAs. The '128' indicates the 128-Kbit density, while '10' denotes the speed grade. The 'JC' suffix specifies the 20-lead PLCC package and commercial temperature range.

Configuration PROMs For FPGAs Replacement Considerations

AT17LV128-10JI

Configuration PROMs For FPGAs FAQ

How does the device handle cascading configurations?

The device uses a Chip Enable Output (CEO) pin that goes Low when the address counter reaches its maximum value, enabling the next device in the chain.

Is the reset polarity fixed?

No, the reset polarity is programmable via four EEPROM bytes during the programming phase.