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The AT22LV10-25SI is a low-voltage UV-erasable programmable logic device (PLD) manufactured by Microchip Technology. It features the familiar 22V10 architecture with 22 inputs, 10 I/Os, and 10 registered outputs. Operating within a 3.0V to 5.5V supply range, this industrial-grade variant (-40°C to +85°C) delivers a maximum propagation delay of 25 ns. The device utilizes CMOS technology for high reliability, offering 200 mA latchup immunity and 2000V ESD protection. It is housed in a 24-lead Small Outline Integrated Circuit (SOIC) package.
Verify that the component is the AT22LV10-25SI variant, which specifies the Industrial temperature range (-40°C to +85°C) and the 24-lead SOIC package. Confirm the presence of the UV-transparent window on the package top, as this indicates the device is UV-erasable and requires handling precautions to prevent unintentional erasure from fluorescent lighting or sunlight.
Select the AT22LV10-25SI when an industrial temperature rating is required alongside a 25 ns speed grade. This part is functionally identical to the commercial AT22LV10-25JC but rated for -40°C to +85°C. If lower power consumption is critical, consider the AT22LV10L-25SI variant, which offers significantly reduced current draw while maintaining the same timing characteristics.
This device belongs to the AT22LV10 family of low-voltage UV EPROM PLDs. It shares the same logic architecture as the standard 22V10 but operates at lower voltages. The 'SI' suffix denotes the specific combination of the 25 ns speed grade and the 24-lead SOIC surface-mount package configuration.
Direct pin-compatible replacements include the AT22LV10-25JI (PLCC package) and AT22LV10-25PI (PDIP package). For lower power applications, the AT22LV10L-25SI is a compatible alternative. Ensure any substitute maintains the UV-erasable characteristic if field reprogramming is necessary.
The entire fuse array is erased using ultraviolet light at a wavelength of 2537 Å. Complete erasure requires a minimum of 20 minutes of exposure using lamps with an intensity of 12,000 µW/cm² spaced one inch away from the chip.
Register preload allows each register to be asynchronously loaded with a high or low state independent of the logic function. This simplifies testing by forcing specific states into the registers to control test sequencing.
All registers are designed to reset to the low state during power-up. This occurs slightly after VCC crosses 2.5V, ensuring deterministic initialization for state machines provided the clock remains stable during the reset period.