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The ATF750CL-15PU is a high-speed, electrically-erasable CPLD from the ATF750C(L) family. It features 24 pins in a Plastic Dual Inline Package (PDIP). The device operates at 5V ± 10% and provides 10 macrocells with 10 I/Os and 12 inputs. Key electrical parameters include a maximum pin-to-pin propagation delay of 15 ns and a maximum operating frequency of 71 MHz under external feedback conditions. It supports D- or T-type flip-flops, programmable pin-keepers, and asynchronous resets.
Verify package type matches the 'PU' suffix indicating a 24-lead PDIP. Confirm temperature range requirements align with the Industrial grade (-40°C to +85°C). Ensure design tools support the ATF750C/L device mnemonic for compilation. Check for RoHS compliance if lead-free assembly is required.
Select this part for applications requiring low power consumption alongside high-speed performance. The CL variant offers lower standby current compared to the standard C series. Ensure the design fits within the 171 total product terms and 42 array inputs limit. Consider the 15 ns delay for timing closure in synchronous systems.
The ATF750CL-15PU belongs to the ATF750C(L) series, which is a superset of the 22V10 architecture. It is backward compatible with ATV750B/BL and ATV750/L devices. The 'L' denotes low-power technology, while '15' indicates the 15 ns speed grade. The 'PU' suffix specifies the plastic DIP package.
Direct replacement for ATV750(L), ATV750B(L), and 22V10 devices. Verify software compiler settings when migrating from older Atmel devices to ensure correct fuse pattern programming.