ATTINY10-TSHR

Overview

The ATTINY10-TSHR is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. It features 1024 bytes of In-System Programmable Flash, 32 bytes of SRAM, and four programmable I/O lines. The device supports speeds up to 12 MHz at 4.5V–5.5V supply voltage. Key peripherals include a 16-bit Timer/Counter with two PWM channels, a 4-channel 8-bit Analog-to-Digital Converter (ADC), an analog comparator, and QTouch library support for capacitive touch sensing. It operates within a voltage range of 1.8V to 5.5V and is available in a 6-pin SOT-23 package.

Feature Summary

• AVR enhanced RISC architecture delivering near 1 MIPS throughput per MHz
• Integrated 4-channel 8-bit ADC and analog comparator
• Supports QTouch library for capacitive touch sensing interfaces
• Multiple low power modes including Idle, ADC Noise Reduction, and Power-down

Applications

• Capacitive touch sensing applications
• Low power industrial control systems
• Battery operated sensor nodes
• Simple logic replacement devices

Procurement Notes

Verify the specific speed grade required for your operating voltage, as performance varies between 1.8V, 2.7V, and 4.5V thresholds. Confirm that the 6-pin SOT-23 package aligns with your PCB layout constraints. Ensure development tools are compatible with legacy Atmel devices if using older programming hardware.

Selection Notes

Select this component when minimal pin count and ultra-low power consumption are critical. The ATtiny10 offers more memory than the ATtiny4 and includes ADC capabilities absent in the ATtiny9. Consider the extended temperature variant if operation beyond 85°C is necessary.

Part Context

This device belongs to the ATtiny4/5/9/10 family of 8-bit AVR microcontrollers manufactured by Microchip Technology (formerly Atmel). These controllers are designed for high performance and low power consumption in space-constrained embedded applications.

Replacement Considerations

ATtiny4-TSHR, ATtiny5-TSHR, ATtiny9-TSHR share the same package and core architecture but differ in memory size or peripheral availability.