ATTINY84V-10MUR

Overview

The ATTINY84V-10MUR is an 8-bit AVR microcontroller featuring 8 KB of in-system programmable Flash, 512 bytes of EEPROM, and 512 bytes of SRAM. It operates at a maximum clock frequency of 10 MHz with a supply voltage range of 1.8 V to 5.5 V. The device includes 12 programmable I/O lines, an 8-channel 10-bit ADC, two timer/counters with PWM channels, and a Universal Serial Interface. It is housed in a 20-pad QFN package.

Feature Summary

• Advanced RISC architecture executing most instructions in a single clock cycle
• In-system programmable non-volatile memory for Flash and EEPROM
• Integrated analog-to-digital converter with differential channel pairs
• Multiple software-selectable low-power sleep modes

Applications

• Battery-powered sensor nodes
• Industrial control systems
• Consumer electronics devices

Procurement Notes

Verify the component status as Not Recommended for New Design (NRND) before finalizing designs. Confirm the specific ordering suffix matches the required package type and tape & reel configuration. Ensure compatibility with existing PCB footprints for the 20-pad QFN package.

Selection Notes

Select this variant when a lower minimum operating voltage of 1.8 V is required compared to standard ATtiny84 models. Verify that the 10 MHz speed grade meets system timing requirements. Consider the NRND status for long-term production planning.

Part Context

This component belongs to the ATtiny24/44/84 family of 8-bit microcontrollers based on the AVR enhanced RISC architecture. The 'V' suffix indicates support for operation down to 1.8 V, while the '10' denotes the 10 MHz speed grade. The 'MUR' suffix specifies the 20-pad QFN package with tape and reel delivery.

Replacement Considerations

ATtiny84V-10MU

FAQ

What is the data retention period for the internal memory?

The datasheet specifies data retention of 20 years at 85°C or 100 years at 25°C.

How many general purpose working registers does the core contain?

The AVR core features 32 general purpose working registers directly connected to the ALU.

Is the device fully static?

Yes, the datasheet lists Fully Static Operation as a key feature of the architecture.