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The C8051F717-GMR is a mixed-signal ISP Flash MCU from the C8051F7xx family, featuring a high-speed 8051 µC core with up to 25 MIPS throughput at a 25 MHz clock. It integrates 16 kB of in-system programmable Flash memory and 512 bytes of internal data RAM. The device includes a capacitance-to-digital converter supporting up to 38 input channels for touch sensing, a 10-bit ADC operating at 500 ksps, and an analog comparator. Digital peripherals include hardware UART, SMBus, SPI, four 16-bit timers, and a Programmable Counter Array. It operates on a supply voltage of 1.8 to 3.6 V within a temperature range of –40 to +85 °C.
Verify the specific suffix 'GMR' against the manufacturer's current documentation to confirm package type and reel specifications. Confirm that the component status remains active, as the datasheet indicates this family is not recommended for new designs. Ensure compatibility with existing PCB footprints for the QFN-24 package before procurement.
Select this model when capacitive touch functionality is required alongside standard mixed-signal processing. The QFN-24 package suits space-constrained designs. Evaluate the 16 kB Flash limit against application firmware size requirements. Consider the 1.8 V minimum supply voltage for battery-powered implementations.
This component belongs to the Silicon Labs C8051F70x/71x series of fully integrated mixed-signal System-on-Chip MCUs. The series combines a high-speed 8051-compatible core with extensive analog and digital peripherals on a single die. The C8051F717 variant specifically targets applications needing capacitive sensing integration.
Consult the official datasheet for alternative part numbers within the C8051F7xx family that offer different pin counts or peripheral configurations. Verify pinout compatibility if substituting with other variants in the same series.
Yes, it features a Capacitance-to-Digital Converter (CS0) that supports buttons, sliders, wheels, and capacitive proximity sensing with up to 38 input channels.
The high-speed 8051 µC core provides up to 25 MIPS throughput when operating at a 25 MHz clock frequency.