CD4013BE

Overview

The CD4013BE is a dual D-type flip-flop from the Texas Instruments 4000B series, housed in a 14-pin PDIP package. It operates on a supply voltage range of 3V to 18V with a maximum propagation delay of 90ns at 15V and 50pF load. The device features positive edge triggering, complementary outputs, and independent set/reset functions. Static current is typically 4µA, with output drive capabilities of 6.8mA high and low. Operating temperature spans -55°C to 125°C.

Feature Summary

• Dual independent D-type flip-flops with positive edge triggering
• Asynchronous set and reset functionality independent of clock
• Complementary Q and Q-bar outputs for versatile logic integration

Applications

• Shift register configurations
• Binary counter circuits
• Frequency division applications

Procurement Notes

Verify the specific suffix 'E' confirms the 14-pin plastic dual in-line package (PDIP). Confirm RoHS compliance status as manufacturing processes evolve. Ensure the source document explicitly lists CD4013BE as an active component, as some distributors may list discontinued variants like BEE4. Cross-reference pinout diagrams against target PCB footprint requirements.

Selection Notes

Select this component when through-hole mounting is required for dual D-type storage. Compare against SOIC variants like CD4013BNSR if surface area is constrained. Verify that the 90ns propagation delay meets system timing constraints. Ensure the 3V-18V operating range aligns with the available power supply rails in the design.

Part Context

Part of the standard 4000B CMOS logic family, widely used for general-purpose digital logic. The CD4013 variant specifically provides two independent flip-flops per package. It serves as a foundational building block for sequential logic designs requiring data storage or state retention in industrial and consumer electronics.

Replacement Considerations

• CD4013BM
• CD4013BMT

FAQ

How are the set and reset functions activated?

Set and reset operations are asynchronous and independent of the clock signal. They are activated by applying a high-level signal to the respective Set or Reset input pins.

What is the trigger mechanism for data transfer?

Data is transferred from the D input to the Q output on the positive-going transition of the clock pulse.